Midterm presentation

1. FPGA Based SAT Solver Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Midterm presentation Started at: Winter 2012 Duration: Semester

2. outline • What is SAT • Reminder - description and goals • Flow diagram • Initial circuit diagram • Resources usage and times • Example simulation results • Live Presentation • Milestones • Gantt diagram

3. What is sat • Boolean Satisfiability Problem • Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true? • e.g., given the formula f=(x1 ˅ x3˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’

4. Reminder – description and goals • Description: • Hardware based SAT Solver • Goals: • Implementing SAT instances into FPGA • Measuring build and run times for benchmark examples • Implementation Time as function of SAT complexity graph • Enabling further development of fast hardware based SAT Solver

5. Flow diagram Programmable File Circuit Description as VHDL CNF Instances Synthesis Conversion Device Programmer FPGA Running SAT Solver PC DE2 Analysis and Timing Report

6. Initial circuit diagram F clk en sOUT timeOUT

7. Resources usage and times • For SAT instance of 20 variables and 91 clauses • 155 Logic Elements • Compile design time : 40 seconds • For SAT instance of 1000 variables and 4250 clauses • 7110 Logic Elements • Compile design time : 43 minutes *Clock frequency is 50M [Hz]

8. Example simulation results • For SAT instance of 20 variables and 91 clauses • Satisfying input: 00101011011101000000

9. Milestones • Whats next: • Testing some benchmark problems • Collecting timing results • Creating a detailed graph of times vs. “size”.

10. Gantt chart