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An Implementation Study on Fault Tolerant LEON-3 Processor System

Z. Stamenkovi ć. An Implementation Study on Fault Tolerant LEON-3 Processor System. Outline. Radiation and fault tolerance System description Implementation details Test results Under way. Reliability Issues in Radiation Environments. Single-event upset (SEU)

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An Implementation Study on Fault Tolerant LEON-3 Processor System

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  1. Z. Stamenković An Implementation Study on Fault Tolerant LEON-3 Processor System

  2. Outline • Radiation and fault tolerance • System description • Implementation details • Test results • Under way

  3. Reliability Issues in Radiation Environments • Single-event upset (SEU) • A change of state caused by a charged particle strike to a sensitive volume in a microelectronic device • Alpha particles (helium-4 nuclei) emitted by radioactive atoms found in packaging materials • Thermal neutrons in certain device materials that are heavily doped with 10B • High-energy terrestrial cosmic rays (play a major role) • SEU-induced latch-up • A failure mechanism of CMOS integrated circuits characterized by excessive current due to parasitic PNPN paths

  4. Fault Tolerance of LEON-3 Processor • SEU tolerance by design (Gaisler Research) • Triple-module-redundancy (TMR) on all flip-flops • Three copies of a flip-flop • Two of three voting on output • Register file error-correction (up to 4 errors per 32-bit word) • Cache RAM error-correction (up to 4 errors per tag or 32-bit word) • Autonomous and software transparent error handling • No timing impact due to error detection or correction • Fault-tolerant memory controller • Provides an Error Detection And Correction Unit (EDAC) • Corrects one and detects two errors • Not immune to SEU-induced latch-up (in present IHP technology)

  5. Scan-I/F FT Add-on Scan Test UART 0 Serial 0 2 kByte I- Cache UART 1 Serial 1 8 x GPIO Bridge LEON_3FT Core 8 Reg. Windows EJTAG GPIO AHB APB 2 kByte D- Cache FT Memory Controller 1 x 24bitTimer FT Add-on EDAC SRAM FLASH LEON-3 Processor System

  6. Implementation Details • Installation of the release • Adaptation of the configuration tool (to include IHP’s library) • Implementation of data and instruction caches • Logic synthesis of the design • Implementation of scan chain • Generation of the chip layout • Simulation (functional, post-synthesis and post-layout net-list) • Scan test vectors generation (ATPG) • Scan test simulation • Adaptation of testbenches • EVCD test vectors generation • Test specification • Documentation

  7. Chip Features

  8. Test System (Gaisler Research) • Target hardware consists of a small mezzanine with Fault Tolerant LEON-3 device mounted on a development board (Pender Electronic Design) • Board communicates with a host system (a laptop PC) over one of the on-chip UARTs

  9. Test Execution (Gaisler Research) • Heavy-ion-error injection • Chamber with the vacuum of 10-2 mbar • Californium (Cf-252) source • Flux of 25 particles/s/cm2 at the device surface for 3 hours • “Paranoia” program makes a large number of calculations and registers any computational error or anomaly • On-chip monitoring logic reported 281 effective SEU errors, of which 99% were corrected • Cross-section for a memory RAM bit was measured to 7.2x10-8 cm2

  10. Under Way Protection against SEU-induced latch-up

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