Nano-sized 2D materials for gate dielectric application

1. Nano-sized 2D materials for gate dielectric application

2. Gate dielectrics High-k gate dielectric Top-down approach (thin-film dielectric) Bottom-up approach (nanosheet dielectric) CaNbO BaSrTiO • Atomically thin • Size-independent ε • Low leakage • → high C Capacitance should be better than 1.5nm SiO2, 1nm of dead layer can be critical Dielectric constant decreased by Low-k interfacial dead layer formation Growth-induced defect Thermal strain Dielectric film (C1) C = εA/t 1/Ctot = 1/C1 + 1/C2 Dead layer (C2) at interface

3. Gate dielectrics Nanosheet synthesis Anistropicnanomaterials often made by using surface energy differences between crystal facets but, Manyuseful dielectric materials have cubic or isotropic crystal structure TBA/MnO2 intercalation compound (example) Exfoliation of layered compound yields atomically thin oxide nanosheets Nanosheets are highly crystalline Exfoliation of layered compound yields atomically thin oxide nanosheets Size of nanosheets Thickness depends on the crystallographic thickness of the starting bulk materials Lateral size depends on the size of the starting bulk materials (sub-micrometer to ~10µm from powder, >100µm from single crystallite)

4. Gate dielectrics Nanosheet integration Applications of the LbL method have been frustrated by defect from Pinhole Overlap Ultrasonication treatment removes overlapping patches to produce a monolayer film Dense tiled nanosheets Monolayer Ti0.87O2 10 layer Ti0.87O2 5 layer Ti0.87O2

5. Gate dielectrics Nanosheet integration Langmuir-Blodgett method Simple and effective approach for organizing 2D nanosheets Nealy perfect mono- and multilayer films Uniformity High density Ca2Nb3O10 Dielectric film has good insulating property Leakage current was ~10 nA/cm2 scale at 1V Main hurdle to be overcomed Produce large amounts of identical size and morphology with a reasonable lateral size (to minimize gap and overlap in assembly)

6. Nanosheets Size uniformity Method 1/2 : synthesis of uniform nanosheets CuS2nanosheets (grown by OLA-based solvothermal) 9nm x 4.5nm LaF2nanosheets (grown by oleic acid-based solvothermal) 16nm x 2nm Self-assembling property of these nanosheets implies uniform size and morphology can minimize overlap and gap This methods are highly effective for size uniformity but have limits: Limit in lateral size Few recipes for limited materials Limit in production scale

7. Nanosheets Size uniformity Method 2/2 : sorting from polydispersenanosheets DGUR (Density Gradient UltracentrifugalRate Separation) Graphene colloid Sucrose solution Quick size separation (5min) Limits: Various morphology (A) before separation (B) Chemically reduced graphene (C)-(E) GO

8. Nanosheets Size uniformity Monodisperse Co(OH)2 Hydrothermal synthesis – Thin, large lateral size sheets As can be seen in examples, recipes for monodispersenanosheets are limited It is difficult to synthesis wanted dielectric nanosheets Conclusion High-k nanosheets dielectric: enables high capacitance with low leakage current → for <20nm gate width miniaturization Monolayer deposition methods were developed and uniform, dense films were deposited Various morphology and lateral size should be overcomed large scale production for applications (Intel’s 22nm 3D trigate transistor)

9. CMOS on paper CMOS with oxide semiconductor, on paper substrate Paper substrate: 1) cost-effective 2) recycleability 3) flexibility Substrate also serves as gate dielectric Oxides are sputterd at R.T. Annealed at 150°C Leakage current is relatively high p-type SnOx : 1.3 cm2/Vs n-type IGZO : 23 cm2/Vs

10. CMOS on paper CMOS with oxide semiconductor, on paper substrate Capacitance of thick paper substrate? – High capacitance of 40 nF/cm2 for 75µm thick paper (εr~1000, ~500nm SiO2) In fiber-based foam-like structure, charges are mobile and paper can acts like electrolyte dielectrics Disadvantages of paper gate dielectric: High-speed driving is limited Surface morphology is rough Relatively high leakage current Capacitance rapidly decreases as frequency increases

11. Paper from nanosheets Graphene oxide paper GO paper can be easily synthesized by simple vacuum filtration of colloidal solution of GO Bulky paper- or membrane can be synthesized from 2D nanosheets GO paper has extreme mechanical property and high flexibility

12. Future works ※ Currently, TFT uses 300~400nm SiNx layer for gate dielectric Same amount of capacitance can be acquired with: 100µm BaTiO3 (εr = 1700) ※ LbL multilayer film is more uniform and dense, but thickness is limited Vacuum-filtered membrane, will contain more gaps and voids in film But leakage current will be suppressed by its film thickness Nanosheets can be synthesized as a form of paper Its capacitance and insulating property can be sufficient for TFT application

13. 350ºC (11/12/27) Experiments Non-hydrolytic sol-gel ZTO Ester elimination → Alkyl halide elimination (Zinc acetate → Zinc chloride) 0.027M SnOtBu + 0.15M ZnCl2 0.027M SnOtBu + 0.15M ZnCl2 MEA

14. Experiment ZnCl2, 100mM (260°C annealing) ZnCl2, 125mM ZnCl2, 150mM ZnCl2, 175mM

15. Experiment XPS : non-hydrolytic sol-gel ZTO Zn2p3 Zn2p1 Sn3d3 Sn3d5 SnCl2 0% SnCl2 20% M-O-M 71.8% → 72.3% O vacancy 15.8% → 17.6% -OH 12.4% → 10.1%