1 / 33

Flex Circuit Design for CCD Application

Flex Circuit Design for CCD Application. ECEN 5004 Jon Mah. Topics. System Description CCD Background Flex Circuit Design Constraints/Issues Thermal Analysis Signal integrity based on transmission line reflections Optimized Design Conclusions. System Description.

oshin
Download Presentation

Flex Circuit Design for CCD Application

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Flex Circuit Design for CCD Application ECEN 5004 Jon Mah

  2. Topics • System Description • CCD Background • Flex Circuit Design Constraints/Issues • Thermal Analysis • Signal integrity based on transmission line reflections • Optimized Design • Conclusions

  3. System Description • Actively cooled CCD using Thermoelectric Cooler • Operating Temperature of -100°C ± 0.1°C • Serial Clock Speed of 1MHz • CCD size is 4096 X 4096pixels • 4 flex circuits • Hermetic, evacuated housing (not pictured) • Concentrate on Base assembly (neglecting external preamps, etc.)

  4. Aside: CCD Background • Starts with exposing the CCD to light. • Charge builds in potential wells via the photoelectric effect Step 1: V1=on, V2=off, V3=off

  5. Moving Charge Using Clock Signals Step 2: V1=on, V2=on, V3=off Step 3: V1=off, V2=on, V3=off Step 5: V1=off, V2=off, V3=on Step 4: V1=off, V2=on, V3=on

  6. Typical 4-Serial Readout • For 4096 X 4096 active area, 2048 X 2048 readout each serial register (neglect overscan) • So, for each parallel shift, 2048 serial shifts • 1MHz is for serial (i.e. parallel is about 0.5KHz)

  7. Serial Register Readout • Pixels read out 1 at a time • Amplifiers, Reset Gate, Last Gates on Serial Register

  8. CCD/Chip Carrier Specifications • Split into 2 Si CCDs (2048 X 4096) • Ceramic Chip Carrier • 3 single parallel clock lines per flex circuit (12 lines) • 3 single serial clock lines per flex circuit (12 lines) • Last gate, reset gate and sum well per flex circuit (12 lines) • 8 input/output bias lines per CCD (16 lines) • 2 shields and 2 ground lines per flex circuit (16 lines) • Total of 68 signal lines • 17 signal lines per flex circuit

  9. CCD/Chip Carrier Marconi Applied Technologies (Secrets of Marconi CCDs June 16-22, 2002)

  10. Flex Circuits • Deposited then etched metal on flexible (polyimide or polyester) substrate • Three basic elements: • Base film • Adhesive • Conductor • Microstrip transmission line • Assume 12cm long • Serial clocks, last gate, reset gate and sum well run at 1MHz and Parallel clocks run at 0.5KHz

  11. Dielectric Films - Polyimide • Material Properties • CTE • Thermal conductivity (k = 0.33W/mK) • Relative Dielectric constant (εr = 4.0) • For an isothermal CCD we want: • Matched CTE with the Adhesive and conductor (prevent delamination or cracking between interfaces) • Low thermal conductivity (maintain thermal isolation of CCD) • Low electrical conductivity (Substrate ground plane unaffected by fluctuations in the chassis)

  12. Adhesive • Material Properties • CTE • Dielectric constant • Thermal conductivity (k = 0.23W/mK) • For isothermal CCD design, we want: • Again, matched CTE with conductors and dielectric film • Low dielectric constant to minimize capacitance • Low thermal conductivity to maintain isothermal CCD

  13. Conductors - Copper • Material properties • CTE • Good Electrical conductivity • Thermal conductivity (390W/mK) • For isothermal CCD design, we want: • Again, matched CTE to adhesive and base/cover films • Good electrical conductivity for lower inductance • Low thermal conductivity to maintain isothermal CCD

  14. Design Considerations • Wire bonds from flex circuit bond pads to CCD bond pads are limited to 25μm diameter gold wire with lengths of about 3mm (neglect for this analysis) • CCD carrier has some thermal resistance (neglect for this analysis) • Neglect convective heating/cooling effects • Geometry limits size of striplines to 2μm thickness • Radiative heating is ~40mW • Neglect heat generated in flex circuit due to power dissipation.

  15. Thermal Performance of Stripline • TEC can handle up to 0.20W to maintain -100°C operating temperature • What are the heat loads from the CCD to the flex circuit • Dynamic • Conduction • Assume that the housing is evacuated (i.e. no convection) • Assume a fixed radiative heat load of 40mW • 100˚C delta across flex (baseplate to CCD) • Fixed adhesive thickness = 0.1μm

  16. Thermoelectric Coolers Marlow MI4012T • 4-stage TEC • Assume that all the heat is removed from the baseplate • Capable of rejecting 0.2W with ΔT = 100˚C Marlow Industries Inc.

  17. Dynamic Heat Load • Most of the heat dissipated on the chip is due to the output amplifier for each serial register • Typical value is about 25mW per amplifier, or 100mW total

  18. Thermal Conduction of Flex Circuits • Fourier Equation • Where k = Thermal Conductivity = 0.33W/mK for polyimide, 0.23W/mK for adhesive, and 390W/mK for Cu A = cross-sectional area = width x thickness ΔT = change in temp across flex circuit = 100K Δx = distance of flex circuit = 12cm

  19. Total Allowable Heat • 100mW from dynamic loads • This leaves 100mW for conduction and radiative heat loads • Assume 15mW per flex circuit • This limits the width of the conductors to about 450μm

  20. Stripline Transmission Line Calculations • Want to match characteristic impedance to the Load • 10Vp-p clock rails • Function of conductor width

  21. Characteristic Impedance for a Microstrip Transmission Line • Z0 for a Microstrip w = width of conductor d = height of polyimide εr = dielectric of polyimide Ramo, S., Whinnery, J., VanDuzer, T. Fields and Waves in Communications Electronics

  22. Reflections • Reflection coefficient is dependent on the load and characteristic impedances • Changes drastically with conductor width • How can we change the load resistance?

  23. Sheet Resistance for Impedance Matching (Geometry)

  24. Sheet Resistance for Impedance Matching (Doping concentration) Red – n-type Blue – p-type http://ece-www.colorado.edu/~bart/book/mobility.htm

  25. Sine wave integrity • Reflection coefficient affects the signal integrity • Design: • 10Vp-p sine wave • load impedance of 10Ω • How dependent is the signal to the conductor width? • Tolerance on fabrication of the conductor width is ~10%

  26. Design Considerations • Conductor width must be less than 450μm • Parallel and Serial clocks need to have different load impedances since they have different frequencies • Minimize sensitivity to reflections by moving the ρ = 0 point higher and to right of the reflection coefficient curve • This can be performed by changing doping and distances between bond pads

  27. Summary • The thermal design constrains the largest conductor width • Impedance matching can be obtained by varying the doping concentration as well as distances of signals to grounds on the CCD • The optimal design for reflection is to have the largest width, which then has the highest tolerance to fabrication errors • Coupling, as well as other effects (reflections due to flex circuits to bond pads to wire bonds to bond pads on the CCD) were neglected in the analysis

More Related