Posted CAS for DDR-II SDRAM

1. Posted CAS Posted CASfor DDR-II SDRAM Bill Gervasi Technology Analyst October, 2002

2. Traditional DDR-I SDRAM CK RAS CAS Data tRCD CAS Latency • RAS and CAS (read/write) issued independently • Controllers must insure the command bus is free • If collisions would occur, next command is delayed • Command streams and arbitration are complex

3. DDR-I Command Stream Command Gap CK RAS CAS RAS CAS CAS RAS 1 0 -1 2 1 0 Data D D D D D D D D -1 -1 -1 -1 0 0 0 0 • Shows string of commands to one DRAM extent • RAS2 delay of 1 clock results in a delay of 2 clocks (to avoid landing on top of CAS1) • Data gap after D1 data caused by command gap Assumed: Page closed policy, tRCD=3, CL=2, BL=4

4. DDR-II Posted CAS for Reads CK RAS CAS Data CAS Latency tRCD Additive Latency READ Read Latency = AL + CL • Delay the internal execution of the CAS command • RAS/CAS commands can be issued back to back

5. DDR-II Posted CAS for Writes CK RAS CAS Data CL - 1 tRCD WRITE Additive Latency Write Latency = RL - 1 • Delay from write command to data tied to CAS Latency • Maintains write-to-read & read-to-write timing relationship

6. DDR-II Command Stream CK CAS RAS CAS RAS CAS RAS 1 0 0 1 2 2 Data D D D D D 0 0 0 0 1 • Shows string of commands to one DRAM extent • RAS2 delay of 1 clock results in a delay of 1 clock (no collision to avoid, no additional delay) • Data gap of 1 command clock between RAS1/CAS1 and RAS2/CAS2 occurs later in time Assumed: Page closed policy, tRCD=3, AL=2, CL=2, BL=4

7. tRCD tRCD tRCD tRCD Open Versus Closed Page RAS CAS/AP RAS CAS/AP RAS CAS/AP • Closed page systems “Auto Precharge” • Requires RAS and tRCD to reopen same row • Open page systems do not issue “Precharge” if there is a good chance the same page will be accessed again • Avoids need for RAS and tRCD RAS CAS CAS CAS CAS CAS PRE

8. Posted CAS with Open Page Data would appear here without Posted CAS CK RAS CAS CAS Data CASLatency AdditiveLatency CASLatency AdditiveLatency Read Latency Read Latency • Additive latency still included though not “needed” • In this case, Posted CAS reduces performance

9. Posted CAS Summary • Closed Page Policy • Allows RAS & CAS to be issued back to back • No impacts to latency (from RAS) • No command collisions • Longer write recovery • Open Page Policy • Not likely to be used due to increased latency (from CAS) • Disable Posted CAS via programming register

10. DDR-II Read to Read, Posted CAS Internal bank to internal bank CK RAS CAS RAS CAS 1 0 0 1 Data D D D D D D D 0 0 0 0 1 1 1 RL Device to device, same databus CK RAS CAS RAS CAS 0 0 1 1 Data D D D D 0 0 0 0 RL Device Handoff Gap

11. DDR-II Read to Write, Posted CAS Minimum interleave, bus limited, applies to all situations CK RAS CAS RAS CAS 0 0 1 1 Data D D D D D D D 1 1 0 0 0 0 1 RL WL

12. DDR-II Write to Read, Posted CAS Internal bank to internal bank CK RAS CAS RAS CAS 1 0 0 1 (CL + 1 + tWTR) Data D D D D 0 0 0 0 WL Device to device, same databus CLK RAS CAS RAS CAS 1 0 0 1 Data D D D D D D 0 0 0 0 1 1 WL W/R Turnaround Gap

13. DDR-II Write to Write, Posted CAS Internal bank to internal bank or device to device with MBT* CK RAS CAS RAS CAS 1 0 0 1 Data D D D D D D D 0 0 0 0 1 1 1 WL Device to device, same data bus with ODT* CK RAS1 CAS1 RAS CAS 0 0 Data D D D D D 1 0 0 0 0 WL ODT Shift Gap * MBT = Motherboard Termination * ODT = On-Die Termination

14. Conclusions: • Posted CAS reduces command bus collisions • Results in higher data throughput • Optimized with WL = RL - 1 for maximum data bus utilization • Can be disabled for open page systems • Simple concept, easy control, great benefit