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Low Power Wireless Design

Low Power Wireless Design. Dr. Ahmad Bahai National Semiconductor. J/Bits/s/Hz. Bits/s/Hz. Design for worst case. Configurable Design. Hybrid. Centralized. New paradigm in Wireless. Power Efficiency. Configurability. Architecture. Distance to IP Network. TX Power. Data Rate.

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Low Power Wireless Design

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  1. Low Power Wireless Design Dr. Ahmad Bahai National Semiconductor

  2. J/Bits/s/Hz Bits/s/Hz Design for worst case Configurable Design Hybrid Centralized New paradigm in Wireless Power Efficiency Configurability Architecture

  3. Distance to IP Network TX Power Data Rate Cellular Miles 100 mW 100s kbps WLAN Yards 10 mW 10s mbps UWB Feet 100s mbps mW Pervasive IP Power efficiency Power = Tx power + Circuit power Tx power ~ Circuit power (1nJ/bit transmission energy- 10 m distance)

  4. Comm Theory, Asym Values Absolute minimum energy for reliable transmission of 1 bit of information Min switching energy for digital gate (1 electron @100mV): 1.6X10-20

  5. Transmission vs. Circuit Energy Communication Theory usually considers Transmission energy only! Transmission Energy Spectral Efficiency But Optimal Bandwidth-time pair?

  6. Total Energy (MQAM)

  7. Platform RF/Analog supporting up to 4 radios Phy Tx/RX MAC layer including ARM and PCI PCI interface

  8. Power profile in WLAN (TX)

  9. Power profile in WLAN (RX)

  10. Channel Effect IMEC Collaboration

  11. Bandwidth Power Mask Interference Data rate BER Channel SiNR Dynamic Range Margin Noise figure Modulation Coding Synchronization MAC State machines Adaptive design Statistical performance Energy QoS Comm Theory Approach

  12. Energy and Throughput Common Approach: Define SINR and capacity as Assume BPSK with BER target of 10e-q, bandwidth W and target data rate of R>C; then we can show that minimal power vector supporting network topology for low SIR can be derived as:

  13. Design Strategy System level approach to low power communication design • Case study: ZigBee • Profile the power consumption • Study effect of multi-layer optimization • A new design strategy

  14. IEEE 802.15.4 PHY • Direct Sequence Spread Spectrum (DSSS) radio • 2Mchip/s OQPSK modulation • 1 symbol = 32-chip PN sequence • 1 symbol = 4 bits • PHY data rate: 250kbps • Transmit power up to 0 dBm BAND COVERAGE DATA RATE CHANNEL(S) 2.4 GHz ISM Worldwide 250 kbps 16 868 MHz Europe 20 kbps 1 915 MHz ISM Americas 40 kbps 10

  15. 802.15.4 spec. summary • Symbol rate and Tx RF accuracy: +/- 40 ppm • Packet Error Rate (PER) • Defined for PSDU of 20x8 bits • Sensitivity: -85 dBm (PER < 1%) • RSSI: sens. level +10 dB, 40 dB range (+/- 6dB) • Max input level: -20 dBm • Jamming resistance (interference performance) • 0 dB for adjacent channels (ref: -82 dBm) • 30 dB for alternate channels (ref: -82 dBm) • Interferer is 802.15.4 compliant interferer • Tx Error Vector Magnitude : < 35% for 1000 chips • Tx PSD: -20 dB or –30 dBm |f-Fc| > 3.5 MHz (rbw 100kHz) • Output power: > -3 dBm (@ max power setting) • Rx-Tx turnaround time: 12 Symbols (192 ms)

  16. ZBIC, one-chip solution ZBIC

  17. 4-state/Transition Energy Profile Power Profile Shutdown 80 nA VDD = 1.8V 970 us 691pJ 194 us 6.63 uJ TX -25 dBm: 8.42 mA -15 dBm: 9.71 mA -10 dBm: 10.9 mA -7 dBm: 12.17 mA -5 dBm: 12.27 mA -3 dBm: 14.63 mA -1 dBm: 15.785 mA 0 dBm: 17.04 mA Idle 396 uA 194 us 6.63 uJ RX 19.6 mA Transition Energy  T(transition) x I(target state) x VDD IMEC/MIT

  18. Larger packet size Transmit power control Network Load Contention Channel Coding Link layer performance Observations Efficiency (energy/bit) changes with:

  19. Power Breakdown Breakdown between the states In high load, the node spends more time in RX than in TX mode! IMEC/MIT

  20. More comprehensive Energy model Energy efficiency metric: TX, RX, Collision, sensing, Transitions, ramp up New model for total energy was used to optimize back off strategy in an ad-hoc network.

  21. Energy Efficient Backoff Standard backoff Proposed backoff Resetting back-off is more energy efficient than DCF backoff due to carrier sensing overhead.

  22. Summary Statistical Performance Analysis: New design paradigm in communication Configurable and low power design: Key Design objectives Multimode/Multi-layer Optimization Analog/mixed signal: critical in power consumption Mixed signal processing and cross layer optimization

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