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Computer Architecture II: Specialized 0909.444.01/02 Fall 2001. Lecture 1 October 25, 2001. John L. Schmalzel Shreekanth Mandayam ECE Department Rowan University http://engineering.rowan.edu/~shreek/fall01/comparch2/. Plan. Intel P4 Quick Review: Integer Representation Sign-Magnitude
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Computer Architecture II: Specialized0909.444.01/02Fall 2001 Lecture 1October 25, 2001 John L. Schmalzel Shreekanth Mandayam ECE Department Rowan University http://engineering.rowan.edu/~shreek/fall01/comparch2/
Plan • Intel P4 • Quick Review: Integer Representation • Sign-Magnitude • Twos Complement • Quick Review: Integer Arithmetic • Floating Point Representation • IEEE 754 Standard • Floating Point Arithmetic • IEEE 754 implementation
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Sign-Magnitude Twos Complement Quick Review:Integer Representation
Twos Complement: Range -2n-1 to 2n-1-1
Biased Exponent Significand/Mantissa/Fraction Sign bit Floating Point: Example 8 bits 23 bits Sign of Mantissa
References • William Stallings, Computer Organization and Architecture, 5th Edition, Prentice-Hall, 2000. • ftp://ftp.prenhall.com/pub/esm/computer_science.s-041/stallings/Slides/COA5e-Slides/ • IA-32 Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture • http://www.intel.com/home/pentium4/