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AFEII-t Platform Test Proposal

AFEII-t Platform Test Proposal. Nov 1, 2005 FTG Paul Rubinov. Goals for platform test. What the platform test is: System test: test integration of ALREADY KNOWN TO WORK AFEIIt with Dzero systems. Seq readout LVDS/trigger 1553 communications Temperature control Ambient temperature

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AFEII-t Platform Test Proposal

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  1. AFEII-tPlatform Test Proposal Nov 1, 2005 FTG Paul Rubinov

  2. Goals for platform test P Rubinov FTG Oct 05 • What the platform test is: • System test: test integration of ALREADY KNOWN TO WORK AFEIIt with Dzero systems. • Seq readout • LVDS/trigger • 1553 communications • Temperature control • Ambient temperature • Power supply interactions • Any surprises

  3. Goals for the platform test (cont.) P Rubinov FTG Oct 05 • What the platform does NOT test: • Again, only known working boards that go to the platform • Mapping of the channels, fiber to readout • Checking the efficiency of the TriP-t • “personality” mapping • Maximum data rate in AFEII mode • Board to board variations for AFEIIt

  4. Goals for platform test (finally!) P Rubinov FTG Oct 05 • Goals: • Check that AFEI power supply is ok for AFEII • Check that seq readout is reliable and stable at ??? Hz • Check that the trigger get the data we sent it! • Do this by comparing VSVX data to trigger data- possibly just counting hits or doublets or just walking ones • Check 1553 communications on a fully loaded bus • Check temperature control calibration and stability • Is it possible to bypass the Phase 5 test stand? • Check that the board is stable at the elevated platform temperatures • Check for (m)any surprises

  5. Platform test where and when P Rubinov FTG Oct 05 • Proposal: 2 to 4 boards in the FPS crate • Full crate • Has trigger connection • Sees light • Has both high gain and low gain chan • Small impact for high Pt physics? • No later than Feb- must not hold up full production • I propose to go with preproduction after successful 4CC test

  6. Platform test P Rubinov FTG Oct 05 • Open questions • Is the trigger system in the FPS mature enough to make this test useful/meaningful? (how long to implement the walking ones test?) • Is there anyone to analyse the data? • Seq data? Trigger data? Timing data? • How long will the boards stay on the platform if they seem to work ok? • Who will decide if they seem to work ok?

  7. Platform test – plan B P Rubinov FTG Oct 05 • Alternatives • Staged platform test • 2 boards in the spare slots – check stability, power supply, temperature, bias, readout. • Move to CFT stereo (or FPS?) – check mapping, efficiency, readout • Move to CFT axial – check trigger system/LVDS/personality • Partial test • Move a fiber cable over from a neighbouring slot- check just one or two modules – to see light during access using LEDs

  8. Platform test – plan B P Rubinov FTG Oct 05 • Consensus platform test proposal • Time in, calibrate the boards on the 4cc • Run boards in combined test stand for a few days • 2 boards in the spare slots – check stability, power supply, readout. For this step we are allowed to not have the online downloads • Before moving them into the real system, we will have to have the calibration machinery working. We will decide where in the system they go based on what we learn from CTS and what we still would like to test.

  9. Platform test important points • Can we time in the AFEII upstairs by comparison to AFEI? We think yes. • We are allowed to download the AFEIIt boards by unplugging the 1553 cable and using our own system

  10. AFEIIt status • 1553 arrives on the board and connects to the 1553 FPGA • Which connects to the PIC microC and HELPER FPGA • PIC and HELPER program/communicate with 4 DFPGA and 8 AFPGA • The DFPGA controls the DISCRIMINATOR readout of the TriP, scrambling the bits appropriately and sending them to the LVDS drivers, which send them to the Mixer/CTT.

  11. The AFPGA controls the analog readout of the TriP. It controls the power, all the clock signals for preamps/amps, pipeline, output muxes, ADCs, programming interface. It takes the data and scrambles it to mimic AFEI, ped subtracts, threshold supresses, stuffs it into a RAM for later readout. All 8 AFPGA form a kind of bucket brigade to read the data out. This data is sent on to the COLLECTOR FPGA for readout.

  12. The COLLECTOR FPGA also receive discriminator data from the DFPGA for the “VSVX” readout. This FPGA also interfaces to the SEQ cable to readout the data and provide control signals to the board. The COLLECTOR FPGA is what actually pushes the data to the sequencer. This can happen either under the control of the SEQ clock, or using the internal AFE clocks.

  13. The whole process has to be precisely orchestrated (timing) both within the AFE board, from FPGA to FPGA and also to the external world, via the Sequencer cable. This is accomplished by the CLOCKGEN FPGA, in combination with 4 PLLs and a VCXO.

  14. The PIC and HELPER FPGA also interface with the DACs, ADCs and MUXes which take care of things like bias setting, measuring the temperature, setting the heater power, measuring the board temperature.

  15. Key to AFEII status • Statements in blue have been tested. • Statements in yellow have been simulated but has not been tested on the board as yet. • Statements in red has not been simulated or tested.

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