Sequential Logic Registers Tutorial

1. Tutorial 2 Sequential Logic

2. Registers • A register is basically a D Flip-Flop • A D Flip Flop has 3 basic ports. D, Q, and Clock

3. Registers • Registers are edge sensitive to the clock • On a rising edge of the clock, the output of the flip flop (Q) takes on the value of the input (D). This is known as ‘clocking in’. • When it’s NOT the rising edge of the clock, Q doesn’t change even if D does • A register is often considered the most basic block of memory, because the value of D is stored in the register until the next clock cycle

4. Sequential Circuits • A sequential circuit is any digital design that has registers in it

5. Processes • In VHDL, sequential logic is described in a process process(clk) begin if rising_edge(clk) q <= d; end if; End process; • The rising_edge (or falling_edge) statement is a key word. Anything assignments in this “if” block is registered.

6. Processes • In a process, inside an ‘if rising_edge’ block, all assignments are registered • This means that on an assignment statement, everything to the LEFT of the <= is the output of a DFF and everything to the RIGHT is the input to a DFF

7. Processes • The previous example described a DFF. Let’s describe something else. If rising_edge(clk) then a <= b; c <= a; end if; • What does the hardware look like?

8. Processes

9. Processes • Let’s mix it up a bit If rising_edge(clk) then a <= b; c <= b; end if • What does the hardware look like?

10. Processes

11. Processes • Let’s put some combinational logic between those registers! If rising_edge(clk) then a <= b and c; d <= a and b; end if; • What does the logic look like?

12. Processes

13. Processes • Registers can also feed back on themselves Process (clk) if rising_edge(clk) then a <= b or c; d <= a xor d; end if; end process; • What does this hardware look like?

14. Processes