1 / 18

Low Power RF/Analog Amplifier Design

Low Power RF/Analog Amplifier Design. Tong Zhang Auburn University. Motivation Design a low power CMOS LNA (Low-Noise Amplifier). Motivation and Design Objective. Design Objective. My Work. This Work Design a 2.4 GHz cascode CMOS LNA.

papina
Download Presentation

Low Power RF/Analog Amplifier Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Low Power RF/Analog Amplifier Design Tong Zhang Auburn University

  2. Motivation Design a low power CMOS LNA (Low-Noise Amplifier) Motivation and Design Objective Design Objective

  3. My Work • This Work • Design a 2.4 GHz cascode CMOS LNA. • Design a low power CMOS LNA with comparable performance. 3. Comparison between the two LNAs.

  4. Tools and Techniques • Tools Virtuoso Schematic Composer and Spectre Simulator from Cadence Design Systems, Inc. • Techniques 0.13 µm CMOS process

  5. Circuit Diagram Comparison Traditional CMOS LNA Low Power CMOS LNA

  6. Schematic of Traditional CMOS LNA

  7. Schematic of Low Power CMOS LNA

  8. Circuit Description • Traditional CMOS LNA • A inductance network (Lg, Ls ) is used for are used for input matching. • A RLC filter network (Lout, Cout, Rout ) is used for selecting the output frequency. 3. Vg1 is biased at 0.53V; Vg2 is biased at 1.7V;Vdd is biased at 2 V.

  9. Circuit Description (cont’) • Low Power CMOS LNA • M2 and P1 operates as inverter-type amplifier stages to make LNA high linearity due to its symmetric structure. • C1 couples the ac signal amplified by M1 to M2, while the source of M2 is bypassed by C2. • 3. Vg1 is biased at 0.5V; Vg2 is biased at 1.3V; Vdd is biased at 2 V.

  10. Simulation Result • Input reflection coefficient (S11) • output reflection coefficient (S22) Traditional CMOS LNA Low Power CMOS LNA

  11. Simulation Result (cont’) • Power gain(S21) • noise figure (NF) Traditional CMOS LNA Low Power CMOS LNA

  12. Simulation Result (cont’) • Reverse isolation(S12) S12=-40dB <-20 S12=-49.3dB<-20 Traditional CMOS LNA Low Power CMOS LNA

  13. Simulation Result Summary

  14. Power Consumption Traditional CMOS LNA P = Idd x Vdd = 3.668mA x 2V = 7.23 mW Low Power CMOS LNA P = Idd x Vdd = 2.147mA x 2V = 4.3 mW Power Reduction = 41.5%

  15. Conclusion Highlights • A current reuse technique is used to decrease power dissipation with increasing amplifier transconductance for the LNA. In my project, for nearly the same power gain, by decreasing gates bias we get 41.5% power reduction • An inverter-type amplifier which has a symmetric structure is used to achieve high linearity for the LNA (not discussed)

  16. Conclusion (cont’) What need to improve? • Input impedance was not well matched, which means the ac signal of the input will not be able to be fully delivered to the output. • Noise figure shows that the noise of output is a little bit large. A different input matching as well as output matching topology may improve the efficiency and minimize noise of the LNA

  17. Reference • Ickjin Kwon and Hyungcheol Shin , “Design of a New Low-Power 2.4 GHz CMOS LNA” , Journal of the Korean Physical Society, Vol.40, No. 1, Jan. 2002, pp. 4-7. • John D. Cressler and Guofu Niu, “Silicon-Germanium Heterojunction Bipolar transistors”, Artech House, inc. Boston, 2002. • Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.

  18. THANKS!

More Related