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Hierarchical Conditional Dependency Graphs for False Path Identification. A.Kountouris, C.Wolinski. Constraints System Description Parameters. Specification : SIGNAL, C, VHDL,. Estimation of: timing size power memory etc. Clock Calculation. HCDG. C VHDL
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Hierarchical Conditional Dependency Graphs for False Path Identification A.Kountouris, C.Wolinski
Constraints System Description Parameters Specification : SIGNAL, C, VHDL, • Estimation of: • timing • size • power • memory • etc. Clock Calculation HCDG C VHDL Assembly for Target Processor • Transformations : • scheduling • partitioning • optimization Interface generation Code Generation Simulation Synthesis Our New Co-design System Under Construction
Parsing • Hierarchization process • redundant clock removal • refining of clock inclusion relations Initial HCDG Treatment of arithmetic relations (rel. graphs) : a > 5 b < 5 a < b Topological Sort a CCFG b 5 Methodology used High-level specification Hardware C, C, VHDL, Signal • Scheduling under constraints • Hardware Resources Sharing • False Path Detection Final HCDG Clock Calculation for each Path in CCFG Conditional Control Flow Graph Mutual Exclusiveness Detection Process
Clocks Nodes correspond to operations that assign values to variables. H1 ?a H1 H1 H3 H2 inc H6 H3 H4 H6 H4 !b H5 H4 ?c • Eachnode is labeled by two clocks : • utilization clock • definition clock H5 H5 Mutual Exclusiveness Detection Process Clock hierarchy implemented as a hierarchy of BDD trees and represents the inclusion relations between clocks If H2 * H3 = false then H2 H3 and H2 H5 ( H5 H3) end if Hierarchical Conditional Dependency Graph H6=H4+H5
JIAN Benchmark process jian(a, b, c, d, e, f, g, x, y) in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port x, y; out port u[8], v[8]; { static T1; static T2[8], T3[8], T4[8], T5[8]; T1 = (a +1 b) < c; T2 = d +2 e; T3 = c +3 1; if (y) { if (T1) u = T3 +4 d; /*u1 */ else if (!x) u = T2 +5 d; /*u2 */ if (!T1 && x) v = T2 +6 e; } else { T4 = T3 +7 e; T5 = T4 +8 f; u = T5 +9 g; /*u3 */ } } Clocks Operations
process jian(a, b, c, d, e, f, g, x, y) process jian(a, b, c, d, e, f, g, x, y) in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port x, y; in port x, y; out port u[8], v[8]; out port u[8], v[8]; { { static T1; static T1; static T2[8], T3[8], T4[8], T5[8]; static T2[8], T3[8], T4[8], T5[8]; T1 = (a + T1 = (a + b) < c; b) < c; 1 1 T2 = d + T2 = d + e; e; 2 2 T3 = c + T3 = c + 1; 1; 3 3 if (y) { if (y) { if (T1) u = T3 + if (T1) u = T3 + d; /*u1 */ d; /*u1 */ 4 4 else if (!x) else if (!x) u = T2 + u = T2 + d; /*u2 */ d; /*u2 */ 5 5 if (!T1 && x) if (!T1 && x) v = T2 + v = T2 + e; e; 6 6 } else { } else { T4 = T3 + T4 = T3 + e; e; 7 7 T5 = T4 + T5 = T4 + f; f; 8 8 u = T5 + u = T5 + g; /*u3 */ g; /*u3 */ 9 9 } } } } JIAN Benchmark
H1 H1 H1 H1 H1 H1 process jian(a, b, c, d, e, f, g, x, y) H1 ?a ?b ?d ?e ?c 1 in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; ?f H1 H1 H1 H1 H1 H1 in port x, y; H1 out port u[8], v[8]; H1 H1 { H1 +2 +3 static T1; +1 H7 H4 static T2[8], T3[8], T4[8], T5[8]; H2 T1 = (a + b) < c; 1 H10 H6 H3 T2 = d + e; H1 2 +5 H9 +4 +7 T3 = c + 1; 3 +6 H10 H6 H3 if (y) { H9 if (T1) u = T3 + d; /*u1 */ 4 H2 H3 H4 H5 else if (!x) u = T2 + d; /*u2 */ H1 H3 5 H9 if (!T1 && x) v = T2 + e; ?g +8 6 !v } else { H6 H7 H8 H1 H3 H9 T4 = T3 + e; 7 H3 T5 = T4 + f; 8 +9 u = T5 + g; /*u3 */ H9 H10 9 H3 } } H5 !u H5 JIAN Benchmark
CCFG H1 H1 H1 H1 H1 H1 H1 ?a ?b ?d ?e ?c 1 ?f N0 Start H1 H1 H1 H1 H1 H1 H1 C01 H1 H1 H1 H1 +2 +3 N1 +1 H7 H2 H4 C11 H2 N2 H10 H6 H3 H1 +5 H9 +4 +7 H7 C21 +6 H10 H6 H3 H3 N3 H6 H10 H9 H9 H2 H3 H4 H5 C31 C22 C32 C12 H1 H3 H9 ?g +8 N4 !v H8 H6 H7 H8 H1 H3 C42 H9 H9 C41 H3 N5 +9 H1 H9 H10 C51 H3 N6 end H5 !u H5 JIAN Benchmark
N0 Start C01 H1 N1 H2 C11 N2 H7 C21 H3 N3 H6 H10 H9 C31 C22 C32 C12 N4 H8 C42 H9 C41 N5 H1 C51 N6 end CCFG JIAN Benchmark STOP Clock Calculation for each Path {path1=C01;clock=H1 OK} {path1=C01,C11;clock=H1*H2 OK} {path1=C01,C11,C21;clock=H1*H2*H7 OK} {path1=C01,C11,C22;clock=H1*H2*H6 OK} {path1=C01,C11,C22;clock=H1*H2*H6 OK path2=C01,C11,C22,C31;clock=H1*H2*H7*H9 OK} {path1=C01,C11,C22;clock=H1*H2*H6 OK path2=C01,C11,C22,C31;clock=H1*H2*H7*H9 OK path3=CO1,C11,C21,C32;clock=H1*H2*H7*H10 OK} {path1=C01,C12;clock=H1*H3 OK path2= C01,C11,C22,C41;clock=H1*H2*H6*H9 NO path3= C01,C11,C22,C31,C41;clock=H1*H2*H7*H9*H9 OK path4= CO1,C11,C21,C32,C41;clock=H1*H2*H7*H10*H9 NO path5= C01,C11,C22,C42;clock=H1*H2*H6*H8 OK path6= C01,C11,C22,C31,C42;clock=H1*H2*H7*H9*H8 OK path7= CO1,C11,C21,C32,C42;clock=H1*H2*H7*H10*H8 OK} {path1=C01,C12;clock=H1*H3 OK path2= C01,C11,C22,C41;clock=H1*H2*H6*H9 NO path3= C01,C11,C22,C31,C41;clock=H1*H2*H7*H9*H9 OK path4= CO1,C11,C21,C32,C41;clock=H1*H2*H7*H10*H9 NO} {path1=C01,C12;clock=H1*H3 OK} {path1=C01,C12,C51;clock=H1*H3 OK path2= C01,C11,C22,C31,C41 ,C51;clock=H1*H2*H7*H9*H9 OK path3= C01,C11,C22,C42 ,C51;clock=H1*H2*H6*H8 OK path4= C01,C11,C22,C31,C42 ,C51;clock=H1*H2*H7*H9*H8 OK path5= CO1,C11,C21,C32,C42 ,C51;clock=H1*H2*H7*H10*H8 OK}}
N0 Start N0 Start C01 H1 C01 H1 N1 N1 H2 H2 C11 C11 N2 N2 H7 H7 C21 C21 H3 H3 N3 N3 H6 H10 H6 H10 H9 H9 C31 C31 C22 C22 C32 C32 C12 C12 N4 N4 H8 H8 C42 C42 H9 H9 C41 C41 N5 N5 H1 H1 C51 C51 N6 end N6 end CCFG CCFG JIAN Benchmark Results :
