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SRS-DTC Links

SRS-DTC Links. WG5 RD51 Miniweek. Alfonso Tarazona Martínez, CERN PH-AID-DT. Outline. 1 . Overview 2. Purpose 3 . Architecture 4. Phase Alignment 5. High-Speed Data 6. Measurements 7. Status.

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SRS-DTC Links

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  1. SRS-DTC Links WG5 RD51 Miniweek Alfonso Tarazona Martínez, CERN PH-AID-DT

  2. Outline 1. Overview 2. Purpose 3. Architecture 4. Phase Alignment 5. High-Speed Data 6. Measurements 7. Status Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 1

  3. 1. Overview 3 x SFP+ connectors (up to 5 Gbps each) CAT7 Shielded Cable 4 x twisted pairs 5 meters max (for now) FECs Pinout RJ-45 Clock  Clk to FEC pin 1-2 Data  Data from FEC pin 4-5 Trigger  Trigger/Commands to FEC pin 3-6 Return Additional line for data, clk synchronization,… pin 7-8 Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 2

  4. 2. Purpose • Provideclock (40 Mhz) • Send/Receivetrigger • Send/Receiveslow control frames • Receivedata fromthedetectors at high-speedrate Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 3

  5. 3. Architecture Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 4

  6. 4. Phase Alignment The 40 Mhzclockisprovidedby TTC chip. Thenthisclockissentfromthe SRU boardtothe FEC board. In thiswayallboardsworkwithsameclockand thewholesystemissynchronized. Isitreallythesameone? No, exactly. Samefrequencybutdifferentphase. Weneedtoalignthephase. HOW? Usinga Digital Dual-Mixer Time Difference (DDMTD)method and a smallNeuronal Network(see R. J. Aliaga, J. M. Monzó, M. Spaggiari, N. Ferrando, R. Gadea and R. J. Colom. “PET SystemSynchronization and TimingResolutionusing High-Speed Data Links”, Real Time Conference (RT), 2010 17th IEEE-NPSS). Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 5

  7. 4. Phase Alignment DDMTD makesitpossibletogettheintroduceddelaybythe cable. In thiswaywe can compensatethatdelay, so therisingedge of thetwoclockisproduced at thesame time. Whenthephasesynchronizationisachievedthereturn line will be free (around ms). Initial Phase Phase After Alignment Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 6

  8. 5. High-Speed Data • High-speedclocks are generatedfrom 40 Mhzclockonthe FEC sidetosend data from FEC boardto SRU board. Thejitter can be a problem in thehigh-speedclocksincethe PLL into FPGA isnot so good. Forthisreason, wehaveincluded a jitter-cleaner chip in the new FEC board (withVirtex 6) • We are capable of sending data at 1 Gbpsusing a CAT7 shielded cable of 5 meters of length • BER (Bit Error Rate) valueis quite good <10-12using a strenuous PRBS (PRBS29) • 8b10b encodingisusedtoachieve DC-balance and distinguishamongdifferenttypes of frames, as triggerframes and commandframes • Therate of data haveto be multiple of the TTC clock, so thephasesynchronizationisachievedmucheasier. Instead of sending at 1 Gbpswewill be data at 960 Mbps, forexample Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 7

  9. 6. Measurements 40 MhzClockJitter (on FEC side) Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 8

  10. 6. Measurements 480 MhzClockJitter (on FEC side) Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 9

  11. 6. Measurements Data Jitter (1 m of cable at 960 Mbps) – EyeDiagram Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 10

  12. 6. Measurements Data Jitter(3 m of cable at 960 Mbps) – EyeDiagram Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 11

  13. 6. Measurements Data Jitter(5 m of cable at 960 Mbps) – EyeDiagram Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 12

  14. 6. Measurements Data Jitter(10 m of cable at 960 Mbps) – EyeDiagram Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 13

  15. 6. Measurements Data Jitter(3 m of cable at 960 Mbps) – Histogram Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 14

  16. 7. Status • Thecurrent status of the DTC link is quite good. Wehaveimplementedthemostdiffucultparts, bothhigh-speedtransmission and phasesynchronization. Nextweekwewillhavereadythefirstversionwiththefollowingfunctionsavailable (fortwo RJ-45 connectors): • Clocksynchronization • Slow control frames (PC  SRU board  FEC board) • Send data at high-speed (960 Mbps) from FEC boardtosendboard • Wekeeponadding new functionsand extendingthecodetocoverthe 40 RJ-45 connectors. Alfonso Tarazona Martínez, CERN WG5 RD51 Miniweek 13 June 2012 15

  17. Thankyouverymuch!!

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