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Position resolution demands fairly small pixels

VERTEX. TRACKER. Push for 300ns timing resolution. Relaxing the timing spec, pixels can be simplified and therefore higher position resolution can be offered to make up for loss of timing (trade-off needs to be argued/proven with physics simulation).

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Position resolution demands fairly small pixels

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  1. VERTEX TRACKER Push for 300ns timing resolution Relaxing the timing spec, pixels can be simplified and therefore higher position resolution can be offered to make up for loss of timing (trade-off needs to be argued/proven with physics simulation) Baseline and only active work seems to be for silicon strips Can we offer something with pixels? Position resolution demands fairly small pixels Power spec and area required sets very low pixel power budgets, eg 2.8uW for 50 micron pixels, 11uW for 100u pixels Rolling shutter during bunch train, egMIMOSA, APSEL, Cherwell Integrating full bunch train, egFPCCD Unacceptable comprimise on spec? Binary (Both) Analog Why are others going to ~20u? 40-50u should give ~5u precision for SNR>10 Mix of analog and binary layers, egMIMOSA30 concept & INTPIX/CNTPIX family Pixel size must be <15um for <5um position resolution Analog, 40-50um VIP targets 20-30u Power budget at 20u pixel is 2.5-5uW – very challenging! Classic preAmp, shaper, comparator architecture not really feasible on monolithic CMOS – too much circuitry to fit in a small pixel boundary without doing something quite extreme in terms of technologu Nobody seems to be doing this!?!? Acceptable comprimise on spec? Power budget is then 20-30uW (1% duty cycle) 10-15uW (2% duty cycle) Classic preAmp, shaper, comparator architecture not really feasible for this power budget for small signal sizes dictated by monolithic topology, Others can achieve this because they have larger signal sizes (bonded detector) hence noise floor can be higher Compare with TPAC (~10uW) in a 50 micron pixel Compare with PIMMS (~50uW) in a 70 micron pixel New design analog CMOS pixel for particle physics 3D solutions egVIP Extreme technology, egchronopix predict they will need 45nm to realise all functionality in a ~15u pixel High cost, Immature trechnology (moderate risk) . Already being pursued Generally not in favour Large dead areas and no analog info Remove empty space (for optical fill factor) could probably reduce to 60 micron pixel at best. High cost, restricted access to technology, already being pursued ? Needs upgrade for analog info Analog sample capacitor(s) read out with digital timestamp – probbaly uses empty space in 70u pixel, no pitch reduction possible! In-pixel ADC, perhaps taking several cycles after a hit to convert, use 2/4 regs for time, 2/4 for analog info? Complex ‘dead-time after hit’ limitation – need a ramp cycling every 10? BXs? Lose the 4th register and add 4 bits ToT to the other three registers – what do we gain in terms of ADC/SNR  position resolution? Very small signals from MAPS! ?

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