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EE 4271 VLSI Design, Fall 2013

EE 4271 VLSI Design, Fall 2013. Static Timing Analysis and Gate Sizing Optimization. Delay Evaluation. 1. Gate delay 2. Interconnect delay. Circuit Model. For an inverter. …. Csink. …. Csink. Gate Resistance.

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EE 4271 VLSI Design, Fall 2013

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  1. EE 4271 VLSI Design, Fall 2013 Static Timing Analysis and Gate Sizing Optimization

  2. Delay Evaluation • 1. Gate delay • 2. Interconnect delay Circuit Delay

  3. Circuit Model • For an inverter … Csink … Csink Circuit Delay

  4. Gate Resistance • Pull-up and pull-down resistors are not a constant. Which value should we choose? • Gate delay also depends on its input signal Circuit Delay

  5. K-Factor Gate Delay • More accurate than RC • Consider input transition time tr (transition rising time) or tf (transition falling time) • Transition time is signal rising/falling time from 10% to 90% • K-factor equation • Delay td=k(tr/f, Ctotal) • Output transition time t’r/f=k’(tr/f, Ctotal) • Synopsis K-factor form: • Delay= a*tr+b*Ctotal+c*tr*Ctotal+d • Obtained from SPICE simulation • Widely used rising time Circuit Delay

  6. Circuit Delay Evaluation - Two Components • Cell delay + interconnect delay • Cell delay is computed using RC • Interconnect delay is computed using Elmore delay Interconnect Cell Cell Circuit Delay

  7. Wire and Gate Models

  8. Step by Step • Model combinational circuit using the previous slide • Starting from primary input gates, compute the arrival time (AT) at each gate, i.e., compute gate delay and interconnect delay • In order to compute the AT at a gate, the ATs of all its input gates need to be computed • Repeat the above process until the ATs at all primary output gates are computed Circuit Delay

  9. Example of Static Timing Analysis • Arrival time (AT): input -> output, take max 1 4 5 3 2 Circuit Delay

  10. Timing Optimization Should we size up this gate to improve timing? • Arrival time (AT): input -> output, take max Circuit Delay

  11. Timing Optimization- II • Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=10, R=1. • If we change the gate with this new one, what is the new delay? Does not change Circuit Delay

  12. Timing Optimization- III • Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=8, R=1. • If we change the gate with this new one, what is the new delay? Circuit Delay

  13. Gate Sizing • This optimization is called gate sizing. Change the gate size (width) in optimization. • 1. Given multiple choices (implementations) per gate type, find a gate implementation at each gate such that the circuit timing is minimized. • 2. Given multiple choices per gate type, find a gate implementation at each gate such that the circuit timing satisfies the target and the total gate area/power is minimized • This formulation is widely used. Circuit Delay

  14. Delay due to Gate Sizing • Suppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size wi, • Gate size wi: R  r/wi, C  cwi • Delay is a function of RC • Delay   RiCj   wi/wj

  15. Combinatorial Circuit Model • Gate size variables x1, x2, x3 • Delay on each gate depends on x a1 a3 x1 a6 D1 D4 D6 D7 a5 a7 a2 a4 Drivers D2 Loads D9 D10 D3 D5 D8 x3 x2

  16. Path Delay • Express path delay in terms of component delay • A component can be a gate or a wire • Delay D for each component • Arrival time afor some components

  17. Gate Sizing • Power/area minimization under delay constraints: • This can be solved efficiently using gpsolve

  18. Gate Sizing using GPSOLVE • Follow the steps in gatesizing.m for the example in the slides of timing analysis and optimization

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