Challenges in Implementation of FPAA/FPGA Mixed-signal Technology

1. Challenges in Implementation of FPAA/FPGA Mixed-signal Technology Lech Znamirowski, lznamiro@top.iinf.polsl.gliwice.pl Adam Ziębiński, adam.ziebinski@polsl.pl Silesian University of Technology, Institute of Informatics International Conference on Engineering Education, July 25–29, 2005, Gliwice, Poland

2. The dynamically reconfigurable mixed-signal systems • Mixed-signal System • controlled by the APMM1 Application Program • controlled by Internal Signals • Fast switching of the internal FPAA Cells

3. using a FPGA with a look-up table and blocks of analog programmable chips (FPAA) The dynamically reconfigurable system

4. Mixed-signal FPAA/FPGA system • CL - Control logic (FPGA) and analog multiplexer, • configuration may contain also initial conditions.

5. The experimental laboratory systems • The XSA-100 Board and the XStend Board • The Anadigm’sAN10DS40 board • The Xilinx Project Navigator • The AnadigmDesigner

6. The experimental station The look-up table of the Application Program APMM1 The FPAA/FPGA mixed-signal system

7. Measurements results • The three-configuration FPAA/FPGA mixed-signal system • Input frequency 80Hz • Details in transition of system output from full-rectifier to inverting amplifier mode • Input frequency 20kHz.

8. Mixed-signal system controlled by internal signals • The dynamically reconfigurable two FPAAs adaptive system: • CL - Control logic (FPGA) and analog multiplexer, • D5Z - processed analog signal, • D2Z - digital control signal to CL • Band-pass filter analog array circuit with the “Control Generator” of the signal D2Z

9. The measurements results • The two-configuration FPAA mixed-signal system • Input frequency 12kHz. • Input frequency 20kHz. • Input frequency 40kHz.

10. The very shorttransients • Result of switching/multiplexing with the delay assuring steady state in the reprogrammed filter

11. Fast switching of the internal FPAA Cells • Track/Compute FPAA integrator

12. The measurements results • Track/Compute integrator output with constant signal in the integrating input • Track/Compute integrator: • details of track to compute transition structure, • details of transition state

13. Conclusions • The time delay for an FPAA application is determined by proper parameters, such as download time and transient states in the interval of switching of CAB • The task assignment may change dynamically when processing requirements change or when a fault in some part of the system is detected. • The experimental, laboratory system assembled in our works is an excellent vehicle to learn about intricacies in performance of dynamically reconfigurable mixed-signal circuits, it is also applied for verification of theoretical predictions, and is used in the students’ education program.

14. References • Palusinski O. A., L. Znamirowski: Track/Compute Structure for Accelerated Dynamic Reconfiguration of Mixed-signal Circuits, Proceedings of the 7-th Int. Conference - Mixed Design of Integrated Circuits and Systems, MIXDES'2000, 15-17 June, Gdynia 2000, pp. 113-116. • Palusinski O. A., L. Znamirowski: Circuit Solution for Accelerated Dynamic Reconfiguration of Mixed-signal Circuits, Proceedings of the 8-th Int. Conference - Mixed Design of Integrated Circuits and Systems, MIXDES'2001, 21-23 June, Zakopane 2001, pp. 115-120. • Palusinski O. A., D. M. Gettman, D. Anderson, H. Anderson et al.: Filtering Applications of Field Programmable Analog Arrays, Journal of Circuits, Systems and Computers, World Scientific Publ., Vol. 8, No. 3, October 1998, pp. 337-353. • Palusinski O. A., S. Vrudhula, L. Znamirowski, D. Humbert: Process Control for Microreactors, Chemical Engineering Progress, Vol. 97, No. 8, August 2001, pp. 60-66. • Reiser C., L. Znamirowski, O. A. Palusinski, S. B. K. Vrudhula et al.: Dynamically Reconfigurable Analog/Digital Hardware Implementation Using FPGA and FPAA Technologies, Proceedings of the ICSEE ’99, 1999 Western MultiConference, The Society for Computer Simulation Intern., San Francisco, California, January 17-20, 1999, pp. 130-135. • L. Znamirowski: SWITCHING. VLSI Structures, Reprogrammable FPAA Structures, Nanostructures, STUDIA INFORMATICA, Vol. 25, No. 4A (60), Gliwice 2004, pp. 1-236. • Znamirowski L.: Dynamic Properties of the Programmable Loop FPAA/Configuration File, 1998 Western MultiConference, (Presented in Session 3 - Field Programmable Analog Arrays (FPAA), ICSEE), The Society for Computer Simulation International, San Diego, California, 11-14 January 1998 (unpublished). Also: L. Znamirowski, O. A. Palusinski (Invention Disclosure, USA): “Modification of FPAA for Adaptive Work in Continuous-Time Operation”, Office of Technology Transfer, University of Arizona, Identification Number 2000-051. • Znamirowski L., O. A. Palusinski: Field Programmable Analog Arrays in Adaptive Filters Applications, Proceedings of the I National Conference - Reprogrammable Digital Systems, Szczecin, March 12-13, 1998, pp. 185-196 (in Polish). • Znamirowski L.., O. A. Palusinski, C. Reiser: Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays, Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, Vol. 31, No. 1, April 2002, pp. 19-30. • Znamirowski L., O. A. Palusinski, S. B. K. Vrudhula: Programmable Analog/Digital Arrays in Control and Simulation, Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, Vol. 39, No. 1, April 2004, pp. 55-73.