Control lines in Computer Architecture

1. Module I Overview of Computer Architecture and Organization

2. Control lines • Used to control access to and the use of address and data lines • They transmit: • Timing Signals: Indicate the validity of address and data • Control Signals: Specify operations to be performed

3. Typical Control lines • Memory Write : causes data on bus to be written to a specified memory location • Memory Read : causes data from addressed location to be placed on bus • I/O Write: causes data on the bus to be placed on addressed I/O port • I/O Read: causes data from the addressed I/O port to be placed on bus

4. Typical Control lines • Transfer ACK : Indicates data have been accepted from or placed on the bus • Bus Request: Indicates a module needs control of the bus • Bus Grant: Indicates bus request is granted • Interrupt Request : Indicates that an interrupt request is pending • Interrupt Acknowledge: Indicates that the pending interrupt request is recognised

5. Typical Control lines • Clock: It is used to synchronize operations • Reset: It initializes all modules

6. Operation of Bus • To send data • Obtain the use of bus • Transfer data via bus • To receive data • Obtain the use of bus • Transfer a request for data • Wait for data from other module

7. Physical Realization of a Bus Architecture • System bus is a number of parallel electrical conductors (metal lines etched in a card) and each of system components taps into bus lines.

8. Physical Realization of a Bus Architecture

9. Multiple Bus Hierarchies • Why? • The more the devices connected, the greater the propagation delay hence less performance • Performance can be improved by increasing data rate and using wider databus • Two Approaches : • Traditional Bus Architecture • High Performance Architecture

10. Traditional Bus Architecture • Isolates processor to memory traffic from I/O traffic. • Cache Memory act as an interface to system bus • Expansion bus interfaces it to external devices

11. Traditional Bus Architecture

12. Traditional Bus Architecture 1. Local bus connects cache memory and support one or more local devices 2. Cache is attached to main memory,isolates main memory and Processor

13. Traditional Bus Architecture 3. Expansion Bus interface buffers data transfers between system bus and I/O controllers

14. Traditional Bus Architecture • 4. Some examples of I/O devices attached: • Network : Local Area Network(LAN) (10 Mbps) • Modem : To connect to Wide Area Network(WAN) • Small Computer System Interface (SCSI): To support local disk drives and peripherals • Serial Port : for printer and Scanner

15. SCSI

16. Fire Wire

17. High Performance Architecture • As I/O performance increased, a high speed architecture named mezzanine architecture is used • A high speed bus is integrated to bring high speed devices closer to processor.

18. High Performance Architecture

19. High Performance Architecture 1) Local bus connects processor to cache controller which is connected to main memory via system bus

20. High Performance Architecture • 1) Cache controller is integrated to a bridge (buffering device) that connects high speed bus • 2) High Speed Bus connects to • High Speed LANs (100 Mbps) • Video and Graphic Workstation controllers • Interface Controllers to local peripheral buses-SCSI and Firewire

21. High Performance Architecture Lower Speed devices are supported with an expansion bus with an interface buffering traffic between the expansion bus and the high speed bus.

22. Advantages • High Speed Bus brings high demand devices close to processor but independent. • Differences in the speed is tolerated • Changes in processor architecture does not affect high speed bus and vice versa

23. Elements of Bus Design • The parameters that classify buses are • Bus Types • Method of Arbitration • Timing • Bus Width • Data Transfer Type

24. Bus Types • Dedicated and Multiplexed • Dedicated • Bus line is permanently assigned to a function or a subset of computer components • It uses multiple buses • Adv: High throughput and less bus contention • Disadv: increased size and cost

25. Bus Types • Multiplexed: • Same bus is used for different functions • E.g. Address and data may be transmitted over same set of lines • Adv: use of few lines saves space and cost • Disadv: complex circuitry is needed and less performance

26. Bus Types • Physically Dedicated: • Multiple buses for a subset of modules. • e.g : All I/O Modules thru I/O Adapter • Adv: High throughput because of less contention • Disadv: Increased size and cost of system.

27. Method of Arbitration • Centralized and Distributed • Centralized : • A single hardware called bus controller allocates time on bus • Distributed : • Each module contains access control logic and modules act together to share the bus

28. Timing • Synchronous and Asynchronous • Synchronous: • Occurrence of events are controlled by clock • All events start at the beginning of clock cycle • Adv: Simple to implement and test • Disadv: less flexible – cannot take advantage of device performance

29. Synchronous

30. Timing • Asynchronous: • Occurrence of one event on bus follows the occurrence of previous event • Adv: fast and slow device can share the bus • Disadv: Difficult to implement

31. Asynchronous : Read

32. Asynchronous : Write

33. Bus Width • Address Bus and Data Bus • Address Bus: • Wider address bus  greater range of locations • Data Bus • Wider data bus  greater number of bits per unit time

34. Data Transfer Type

35. Multiplexed Address/Data Bus

36. Dedicated Address/Data Bus

37. Read Modify Write • Read followed by immediate write to the same address • Used to protect shared memory resources

38. Read After Write • Write is immediately followed by Read • It is for checking purpose

39. Block Data Transfer • One address cycle is followed by n data cycles

40. End of Module I