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ELEC7250 VLSI Testing: Final Project

This project focuses on the VLSI testing process, including the development of a compiler, logic simulator, and a parallel approach for logic simulation. The results obtained from the simulation are demonstrated on a C17 circuit.

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ELEC7250 VLSI Testing: Final Project

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  1. ELEC7250 VLSI Testing:Final Project Andrew White ELEC7250: White

  2. Overview • Problem Description • Plan • Results • Demonstration ELEC7250: White

  3. Plan • Compiler • Hierarchical bench formats are flattened • Logic Simulator • Used simulation table and test vectors • Two states (1,0) ELEC7250: White

  4. Plan • Algorithm • Input vector is propogated through to the output • Traverse through the gates in levels ELEC7250: White

  5. Results ELEC7250: White

  6. Results ELEC7250: White

  7. Plan • Due to long logic simulations • Parallelize the problem • Parallel Approach • Same algorithm as the sequential approach • Main node broadcasts the simulation table to all other nodes • Main node reads in test vector file and evenly distributes vectors to all other nodes • Each node computes vector values and reports the results to the main node ELEC7250: White

  8. Results ELEC7250: White

  9. Fault Diagnosis • Find faulty vector • Find faulty outputs • Algorithm complexity ELEC7250: White

  10. Demonstration C17 Circuit ELEC7250: White

  11. Conclusion Questions/Comments? ELEC7250: White

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