FPIX2: A rad-hard pixel readout chip for BTeV

1. FPIX2: A rad-hard pixel readout chip for BTeV f David Christian Fermilab Vertex 2000 Homestead September 14, 2000

2. New Fermilab collider experiment (approved in June, 2000) • Will be installed in a new interaction region at C0 • startup ~ 2006-2007 • Primary goals: study of CP violation, mixing • & rare decays in b and c systems • “Two arm” forward spectrometer: central dipole with pixel planes • in vacuum – as close to the beam as radiation damage will allow • Level 1 trigger based on tracks & vertices reconstructed using pixel data Vertex 2000 David Christian p2

3. Pixel readout chip for BTeV: requirements • Radiation hard • Optimized for 132 ns crossing time • Able to tolerate large sensor leakage current • High speed zero-suppressed readout • We expect the chip we develop for BTeV to be • suitable for use by CDF and D0 also David Christian p3 Vertex 2000

4. FPIX Designers Abderrezak Mekkaoui: Lead engineer (analog design + overall responsibility) Jim Hoff: Digital design David Christian p4 Vertex 2000

5. FPIX Roadmap • Pixel size = 50m x 400m (matches ATLAS n+ on n test sensors) • Target rad-hard technology = Honeywell 0.5m CMOS (SOI) • (3 metal, 3.3V) (1 metal layer used for shield between sensor & R/O chip) • FPIX0 (1997) HP 0.8m CMOS • Close to final analog front end • R/O pixel includes a peak sensor – digitized off chip • Array size = 12 x 64 • Bench tests and beam tests • FPIX1 (1998) HP 0.5m CMOS • Optimized front end • 4 comparators per cell (2-bit FADC) • New fast R/O architecture, allows both self-triggered and externally-triggered operation • Array size = 18 x 160 • Bench tests and beam tests • Then (Dec, 1998), a change of plans • Try to use deep-submicron CMOS • All subsequent prototypes should be rad-hard. David Christian p5 Vertex 2000

6. FPIX2 Roadmap • 0.25m CMOS • (5 metal [6 possible], 2.5V) • Design for 2 vendors (“lowest common denominator” design rules): • “CERN” – Very favorable contract, but problems with US Gov. restrictions • Taiwan Semiconductor Manufacturing Corp (TSMC) – Available through MOSIS • PreFPIX2-T (1999) TSMC 0.25m CMOS • New analog front end, with new leakage current compensation strategy • 8 comparators per cell (3-bit FADC); no EOC logic included • Array size = 2 x 160 • Bench tests (radiation exposure) • PreFPIX2-I (2000) “CERN” 0.25m CMOS • Same front end • Complete “core” – including new, simplified EOC & R/O (self-triggered only) • Array size = 18 x 32 • PreFPIX2-T2 (2000) TSMC 0.25m CMOS • New programming interface • Internal DAC’s – no external currents required; only external voltages are 2.5V & ground. • Array size = 18 x 64 • FPIX2 (2001) 0.25m CMOS - Final BTeV R/O chip!!?? David Christian p6 Vertex 2000

7. FPIX0/FPIX1 front end* First stage feedback element in box:“Synthetic Resistor” = transistor which acts as a resistor for small signals and as a constant current source (discharging the feedback capacitor) for large signals (or large leakage current). Cinj Vin 50 W to grnd n unit cell boundary Pixel detector p -V(detector bias) Chip boundary * See Blanquart, et al. NIMA 395, p313 (1997) David Christian p7 Vertex 2000

8. High gain cell (9,0) I_fb = 7 nA Leakage current ~ 0 Leakage current ~20 nA/pixel High gain cell (9,0) I_fb = 0.5 nA Leakage current ~ 100 nA/pixel Leakage current ~ 0; I_fb = 7 nA Leakage current ~20 nA/pixel FPIX0 feedback & leakage current compensation FPIX0 Insensitivity to leakage current: High gain cell can be adjusted so that rise time & amplitude with ~20 nA/pixel of leakage current match the rise time & amplitude with no leakage current. David Christian p8 Vertex 2000

9. Sensor Inject Test FPIX1 front end layout Vdda Iff Bump bond Pad (feedback cap is underneath) cascode feedback and leakage current compensation transistors: NOTE aspect ratio! charge injection capacitor 1st transistor David Christian p9 Vertex 2000

10. Radiation damage to CMOS transistors Positive charge trapped in the oxide layer effectively biases the transistors. Gate oxide Gate n+ n+ Source (normally connected to gnd) Drain p bulk Conductive channel is induced by positive voltage applied to the gate “Threshold voltage” shifts with exposure to radiation BUT, the effect gets smaller as the oxide gets thinner (with smaller feature size) … by 0.25m the threshold shifts are small enough to be “benign.” David Christian p10 Vertex 2000

11. Radiation induced leakage current Trapped charge in the field oxide also causes leakage current in nmos devices by inducing an n-channel in the p-bulk. source drain pmos leakage current does not increase (glass charges +; doesn’t induce a p-channel). David Christian p11 Vertex 2000

12. Rad-hard nfet layout (very schematic!) “gate all around” layout (guard rings to prevent latchup not shown) Large W/L is “easy” Small W/L is hard Or, impossible! David Christian p12 Vertex 2000

13. Sensor Inject Test FPIX1 front end layout Vdda Iff Bump bond Pad (feedback cap is underneath) cascode feedback and leakage current compensation transistors: NOTE aspect ratio! charge injection capacitor 1st transistor David Christian p13 Vertex 2000

14. FPIX2 feedback solution • One NMOS feedback transistor biased by a global voltage VFF. • VFF generated such as to track (to the 1st order) the preamp DC level shifts due to global changes (process, temperature…) • Feedback is current controlled as before. This current can be much higher than in the previous scheme. • It is more reliable to work with higher currents. • Leakage current compensation assured by a separate scheme (next slide). David Christian p14 Vertex 2000

15. FPIX2 leakage current compensation • Compensates one polarity • only (n+ on n sensor) • Differential amplifier in feedback must • have VERY low bandwidth! David Christian p15 Vertex 2000

16. Vdda - + Vff - + Sensor Inject Test Vref (pre)FPIX2 front end layout Capacitors used to limit frequency response of op amp in Leakage current compensation circuit charge Injection capacitor Bump bond Pad (feedback cap is underneath) leakage current compensation op amp cascode 1st transistor feedback resistor (transistor) David Christian p16 Vertex 2000

17. Qin=3260e- channel R. 3 different feedback currents. (pre)FPIX2 pulse shapes David Christian p17 Vertex 2000

18. (pre)FPIX2 leakage current compensation After the first nA no change in the response is observed ! David Christian p18 Vertex 2000

19. (pre)FPIX2 Irradiation Tests • Just starting irradiation tests! • 1st test used 60Co source at Argonne • After ~33 MRad: • Circuits are fully functional • No degradation in speed • (inferred from kill/inject shift register operation) • Less than 10% change in analog power dissipation; • less after irradiation. • (as expected; due to small VT change in PMOS) David Christian p19 Vertex 2000

20. (pre)FPIX2: front end response, before and after irradiation No change in settings (bias voltages, feedback current,…) before/after irradiation David Christian p20 Vertex 2000

21. (pre)FPIX2 Noise and discriminator threshold distributions => Practically no change in noise and threshold dispersion. => 200 e- change in the threshold voltage. David Christian p21 Vertex 2000

22. Next Steps • Irradiation of preFPIX2 chips bump bonded to sensors using protons • (Indiana University cyclotron – 200 MeV): • Total dose effects • Single event effects • Latchup • Single event upset (single bit errors) • Tests of preFPIX2-T2 • DAC’s • VLDS I/O • Final Specification of FPIX2 • Array size (18 x 160?) • Output format • serialized, high speed VLDS? • point to point? • drive signals out of high-radiation environment? David Christian p22 Vertex 2000