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Ceng 450 Project

Ceng 450 Project. Pinout of Processor. Interrupt is optional. in_port[7:0]. Processor. out_port[7:0]. clock. rst. interrupt. Instruction Format. Three types of instructions A-Format e.g. arithmetic instructions B-Format e.g. branch instructions L-Format

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Ceng 450 Project

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  1. Ceng 450 Project

  2. Pinout of Processor • Interrupt is optional in_port[7:0] Processor out_port[7:0] clock rst interrupt

  3. Instruction Format • Three types of instructions • A-Format • e.g. arithmetic instructions • B-Format • e.g. branch instructions • L-Format • e.g. load and store instructions

  4. A-Format Instructions Arithmetic Instructions: 7 4 3 2 1 0 Op-Code ra rb e.g.: ADD R[2], R[1] 7 4 3 2 1 0 01 0100 10

  5. B-Format Instructions Branch Instructions: 7 4 3 2 1 0 Op-Code brx rb e.g.: Br R[3] 7 4 3 2 1 0 11 1001 00

  6. Subroutine … … br.sub … … return subroutine:

  7. Subroutine • Link Register (LR): a dedicated register for subroutine call&return • br.sub: PC+1 is loaded into LR … … br.sub … … return 1B PC: PC+1 0X1B: 1C LR: 0X1C: subroutine:

  8. Subroutine • LR: a dedicated register for br.sub instructions • br.sub: PC+1 is loaded into LR • return: PC is loaded with LR … … br.sub … … return 9B PC: 0X1B: 1C LR: 0X1C: subroutine: 0X9B:

  9. Subroutine • LR: a dedicated register for br.sub instructions • br.sub: PC+1 is loaded into LR • return: PC is loaded with LR … … br.sub … … return 1C PC: 0X1B: 1C LR: 0X1C: subroutine: 0X9B:

  10. L-Format Load/Store Instructions: 7 4 3 2 1 0 Op-Code ra First address: ea/imm Second address: e.g.: load R[2], 0xA2 7 4 3 2 1 0 00 0001 10 A2

  11. Project • A processor that executes every program written in the instruction set

  12. Processor Architecture • 1)Datapath • Includes components, alu, register file, memory, … • 2)Controller • Controls flow of instruction and data in datapath Datapath Controller

  13. Instruction Memory We need a container to hold instructions Memory

  14. Register File A place for R[0]~R[3] Reg File Memory

  15. ALU Alu A unit for arithmetic calculations Reg File Memory

  16. ALU Data Memory A unit that holds data Reg File Memory Memory

  17. MEM/WB ID/EX EX/MEM IF/ID ALU Pipeline Architecture To break critical path Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory

  18. MEM/WB ID/EX EX/MEM IF/ID ALU 5-Stages Datapath Up to now, design of main components Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory

  19. MEM/WB ID/EX EX/MEM IF/ID ALU 5-Stages Datapath Up to now, design of main components Complete the datapath for every instruction gradually Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory

  20. MEM/WB ID/EX EX/MEM IF/ID ALU 5-Stages Datapath Up to now, design of main components Complete the datapath for every instruction gradually e.g. ADD instruction Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory

  21. MEM/WB ID/EX EX/MEM IF/ID Instruction Fetch Execute Memory Access Decode Write Back Address ALU Reg File Memory Memory PC A component that holds address of Inst. Memory (PC)

  22. PC Memory Address Instruction Fetch IF/ID Register 7 Op-Code 4 3 ra 2 1 rb 0

  23. MEM/WB ID/EX EX/MEM IF/ID Address ALU ADD Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory Datapath

  24. Decode IF/ID Register ID/EX Decode Reg File rd_data1 rd_index1 7 8 RD1 Op-Code 2 rd_data2 rd_index2 4 8 RD2 3 ra 2 1 2 rb 0

  25. MEM/WB ID/EX EX/MEM IF/ID Address ALU ADD Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory Datapath

  26. ALU Execution Stage ID/EX EX/MEM mode op1 RD1 Alu Result AR op2 RD2

  27. MEM/WB ID/EX EX/MEM IF/ID Address ALU ADD Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory

  28. MEM/WB ID/EX EX/MEM IF/ID Address ALU Memory Access Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory AR

  29. MEM/WB ID/EX EX/MEM IF/ID Address ALU Write Back Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory AR

  30. MEM/WB ID/EX Write Back Write Back Reg File rd_date1 rd_index1 rd_data2 rd_index2 Write Data AR

  31. MEM/WB ID/EX Write Back Write Back ADD R[2], R[1] Reg File Data Register 1 Register No.1 Data Register 2 Register No.2 Write Data AR Which register

  32. Address Memory Address Instruction Revising Our Design IF/ID Register 7 Op-Code 4 3 ra 2 1 rb 0

  33. MEM/WB ID/EX EX/MEM IF/ID Address ALU Write Back Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory AR ra ra Data

  34. MEM/WB ID/EX EX/MEM IF/ID Address ALU Write Back Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory AR ra ra ra Data

  35. MEM/WB ID/EX EX/MEM IF/ID Address ALU Write Back Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory AR ra ra ra ra Data

  36. MEM/WB ID/EX EX/MEM IF/ID Address ALU Write Back Instruction Fetch Execute Memory Access Decode Write Back Reg File Memory Memory AR ra ra ra ra Register No. Data

  37. Other Instructions • We should repeat similar steps for other instructions

  38. Controller 7 DR1 rd_date1 rd_index1 Op-Code 2 Register File rd_data2 rd_index2 4 3 DR2 ra 2 1 2 rb 0 ALU Mode Controller Mem Opr WB Opr

  39. ALU Execute ID/EX EX/MEM op1 DR1 AR Alu Result op1 DR2 Mem Opr ALU Mode WB Opr Mem Opr WB Opr

  40. Memory Access EX/MEM MEM/WB Memory Access ADD R[2], R[1] Mem Opr: Write_En = 0 Mem Adr Memory Mem Data Mem Opr Wr_En WB Opr WB Opr

  41. ID/EX EX/MEM ALU Write Back Execute Memory Access Decode Write Back Reg File Memory wr_en WB Opr AR ra ra ra ra Register No. Register Value

  42. Controller Design Controller Base on Control Signals in Data-Path Instruction from IR Flags Control Signals To DataPath Components

  43. State Machine rst Deactivate control signals reset=1 decode … Op=add wr_enable =1 Op=load

  44. rst reset=1 decode Op=add Op=load State Machine Implementation parameter [3:0] RESET=0,DECODE=1; always @(negedge clk) if(rst) begin state = RESET; //deactivate all control signals end else begin case(state) RESET: begin state=DECODE; end DECODE: begin if(opcode=ADD) … end default: state=RESET; endcase end

  45. Implementation Strategy • First Design Datapath • Design Controller base on Data-Path • Connect Controller and Data-Path

  46. Designing Datapath • Necessary Components • Program Counter • Instruction/Data Memory • ALU • Register File • ….

  47. Datapath Hierarchy Start your design from Bottom Modules

  48. ALU Simulate each Component • Post-Route Simulation 01110111 111101101 Is it Correct? 01000110 Test Vectors Add

  49. ALU Wiring CPU (Top Module) Data Path Reg. File Memory PC Controller Data Signals Control Signals

  50. Debugging • Hazards Because of Pipeline • Data Hazard • Control Hazard • Simulating Complete CPU • Implementation (Pin Assignment)

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