A Fast, Self-stabilizing, Integrated Boost DC-DC Converter Some System & IC Design

1. A Fast, Self-stabilizing, Integrated • Boost DC-DC Converter • Some System & IC Design • Considerations • Neeraj Keskar • Advisor: Prof. Gabriel A. Rincón-Mora • Analog and Power IC Design Lab • School of Electrical and Computer Engineering • Georgia Institute of Technology • April 03, 2006

2. Motivation • Dependence of converter frequency response on passives • Tolerances in capacitor ESR, ESL values • Variations in inductor, capacitor values per design • IC solution for frequency compensation required because • Reduction in design time • Reduction in part count, board size, cost • Ease of design • Need to have IC solution that will give frequency compensation: stability and fast transient response independent of external components • Hysteretic (or SD) control provides a way !

3. Hysteretic Buck Converter • Hysteretic (or SD) control allows the buck converter to achieve: • Wide filter LC compliance, i.e., stability range • Fast transient response limited by filter slew rate • Simple control scheme

4. Proposed Hysteretic (SD) Boost Converter Proposed converter operates through two paths: • Main path – Low bandwidth, operates during steady-state • Bypass path – High bandwidth, operates during transients

5. Proposed Converter Operation Bypass Path Main Path Startup & load/line transients After reaching steady- state Entry Inductor current > IOUT/(1-D) = IOUT/(1-D) VOUT ripple High (~ ± 1%) Low (~ ± 0.2%) High Low Bandwidth

6. Important Design Considerations 1. Steady-state switching frequency determined by inductor current ripple KI >> KV close to switching frequency ( ~ 1 MHz) KI must have high bandwidth (3 dB BW ~ 10 MHz) 2. Good DC voltage regulation KV >> KI at low frequencies ( ~ DC) Both KV and KI must be functions of frequency 3. Comparators Q1, Q2, and Q3 use same input voltages (VS and VREF) Input offset voltages of Q1, Q2, and Q3 must be correlated Low effective offset voltages 4. High BW feedback paths in standard CMOS process, on-chip switches Noise concerns

7. Planned Implementation • Forseen benefits: • Differential processing & • Wider hysteresis, hence • improved noise immunity • Preamplifier KV1 helps correlate input offsets of Q1, Q2, and Q3 without reduction in bandwidth • Forseen drawbacks: • Higher circuit complexity, transistor count, and bias currents • Common-mode feedback issues

8. Preamplifier Realization If Gm1 = Gm2 = Gm, and Gm(R1 + R2) >> 1, then VO/(VREF – VS) ≈ (1 + R1/R2) • Fully differential amplifier with accurate closed-loop gain • Common-mode stabilization achieved through resistors R1 and R2 • Voltage-sense node VS and reference node VREF not loaded

9. Summing Comparator • Low DC gain, high BW path KI with high-frequency pole and zero • High DC gain, low BW path KV with low-frequency pole • Gains KI and KV need tight variations, since they determine switching frequency

10. Gm-Cell Implementation • Accurate voltage gain set by choice of input and output resistors • Maximum bandwidth utilization of the opamp in unity-gain configuration • Frequency responses of KI and KV easily implemented

11. Summary • The motivation for this research is to implement a boost converter circuit and control technique that enables wide LC compliance and fast transient response • A new multi-path control strategy was introduced in boost DC-DC converters, combining speed advantages of hysteretic control and low steady-state ripple of sliding-mode control • Design considerations for the proposed control topology were discussed • Differential mode voltage processing was employed through a closed- loop, fully-differential preamplifier • IC design issues were looked at and possible block design options were shown