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On the Decreasing Significance of Large Standard Cells in Technology Mapping

On the Decreasing Significance of Large Standard Cells in Technology Mapping. Jae-sun Seo, Igor L. Markov, Dennis Sylvester, and David Blaauw ICCAD 2008. Outline. Introduction Experimental Results Analysis of single paths Evaluating utility of large cells in technology mapping Conclusion.

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On the Decreasing Significance of Large Standard Cells in Technology Mapping

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  1. On the Decreasing Significance of Large Standard Cells in Technology Mapping Jae-sun Seo, Igor L. Markov, Dennis Sylvester, and David Blaauw ICCAD 2008

  2. Outline • Introduction • Experimental Results • Analysis of single paths • Evaluating utility of large cells in technology mapping • Conclusion

  3. Introduction • Over several decades, technology mapping has been extremely useful for reducing the device area of complex logic • While technology mapping seeks to minimize device count, the bulk of critical path delay has shifted from gates to wires in the last 5 years

  4. Introduction • Motivation • The literature on buffer insertion that improves circuit performance by adding a large number of one-input one-output gate (buffers and inverters) that do not perform any logic operation • The literature on functional technology mapping, which clusters logic into 5-15 input gates, improving area, but does not evaluate overall circuit performance with respect to current technology nodes

  5. Introduction • Drawbacks of large standard cells • Large standard cells -> fewer cells, but longer individual wires • To many large cells leads to • Worse delay, worse congestion • Non-monotonic interconnects • More buffers added post-placement

  6. Introduction • Avoiding large standard cells • 1-inputs or 2-inputs cells are sufficient to implement logic AND2AND3 AND4 AO AOIBUFDFFFA HAINVMUX2MUX3 MUX4NAND2NAND3 NAND4 NOR2 NOR3 NOR4 OA OAIOR2OR3 OR4 XOR2XOR3XNOR2XNOR3 List of std. cells from library Cell: 2-input or less Cell: 3-input or more

  7. Introduction • Limit the use of large standard cells (3+ inputs) • Expected outcomes • Reduce wire delay at the expense of gate area • Fewer long wires -> fewer buffers inserted during timing optimization • Essentially converting wire delay back to gate delay

  8. Experimental Results • Analysis of single paths

  9. Experimental Results

  10. Experimental Results

  11. Experimental Results • Analysis of large circuits

  12. Experimental Results

  13. Experimental Results

  14. Experimental Results

  15. Experimental Results

  16. Experimental Results

  17. Conclusion

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