ELE22MIC Lecture 10 & 11

1. ELE22MIC Lecture 10 & 11 • Serial Communications • Serial Data Formats - RS232 • 6850 ACIA • HC-COM’s Serial Port - 6551 • IBM PC UART: The 16550 & 16554 • RS232 / ITU V.24 / EIA232 • Sample Interrupt Service Routine (ISR)

2. Serial Data Transmission (1) • Serial I/O is the transmission of data over a single communication line. • Cheaper than parallel • Data is moved sequentially one bit at a time. • Requires a conversion from parallel data format to serial format. • This conversion is normally performed by a shift register driven by a clock.

3. Serial Data Transmission (2) • At the receiving end, data must be reconstructed back into parallel format. • Some method is required to identify bit boundaries. • i.e.: how do you differentiate between 000 and 0000?

4. Serial Data Transmission (3) • Two methods: • Synchronous Transmission • Use a common clock to synchronise the receiver with the transmitter. • Therefore requires a separate tine to carry the clock. • Asynchronous Transmission • The receiver and transmitter has separate, independent, accurate local clocks.

5. Synchronous Serial Data Transmission(4) • Synchronous Transmission is used with the Serial Peripheral Interface (SPI) • See lecture 11. • Uses 4 wires: • Clock • Data • Select# • Ground

6. Asynchronous Serial Data Transmission(1) • RS232 Voltage Levels & Data Format • Line Transciever with Charge Pump - • the MAX232 series. • Serial Data Format • Start Bit, Data Bits, Parity, Stop Bits • Errors: Framing, Overrun, False Start • The 6850 ACIA (Asynchronous Communications Interface Adapter) • AKA: UART (Universal Asynchronous Receiver Transmitter) or ACE (Asynchronous Communications Element) • The RS232 Transmission Distance Limits

7. Clock Synchronisation (1) • The receiver phase locks its local clock to the transmitter's clock by detecting the start bit and stop bits of a serial frame. • Thus it does not require a separate clock line as the data line contains timing information. • If the data is sampled in the mid-point of each bit the clock error less than to 5% can be tolerated with communication remaining error-free between transmitter and receiver.

8. RS232 - Data Format

9. Clock Synchronisation (2) • Start bit signifies the beginning of the frame • Stop bit(s) identify the end of the frame • If the stop bits are received incorrectly it is assumed that the receiver’s clock has drifted out of phase, or some other error has occurred, and a FRAMING ERROR is declared

10. Serial Data Bit Sampling • The signal is sampled by the ACIA in the middle of each bit period.

11. Serial Communication Speed • The rate at which data is transmitted is called the bit-rate • Bit-rate is measured in bits per second. • Baud rate refers to the rate per second of the bit symbols used to transmit the serial data. • i.e.: it includes the synchronisation items: start bit & stop bit(s). For example: If using 10 bit symbols per 8 bit character at 9600 baud equates to a bit rate of 7680 data bits per second (or 960 Bytes per second).

12. Serial Data Bit Error Detection • In any data transfer there is the potential for bit-errors. Parity can be used as a check that the correct bit pattern is received. • Parity calculation involves adding the “1” bits in a frame together. • Even Parity • Adding all bits in frame + parity => ‘0’ • Odd Parity • Adding all bits in frame + parity => ‘1’

13. Serial Data Bit Error Detection

14. Bit Error Rate (BER) (1) • The Bit Error Rate - Probability of bit error - is the number of bit errors measured at the receiver through a communication system. The transmission channel may be Radio, Optical Fibre, Copper Cable, etc. • In analog communications the important unit of measure is the Signal to Noise ratio. • These measures are useful to characterise a system and can be measured or simulated.

15. Bit Error Rate (BER) (2) • If the quality of the system is high, the single bit error rate may be measured in years. In this case a single parity bit would be sufficient to determine data errors & re-transmission could recover the correct data. • The probability of double-bit errors would become negligable. Double-bit errors cannot be detected using a single parity bit.

16. Improving Noise Immunity • One way of improving noise immunity: sample multiple times through each bit and at each sample time, check the status of each bit. Take the most common value of the sample as the bit value.

17. 6850 : Status Register 0 RDRF Receive Data Register Full 1 TDRE Transmit Data Register Empty 2 DCD Data Carrier Detect 3 CTS Clear To Send 4 FE Framing Error 5 OVRN Receiver Overrun 6 PE Parity Error 7 IRQ IRQ pending

18. 6850 : Bus Interface

19. 6850 : Control Register Clock divisor: 0 Counter Divisor Select 1 1 Counter Divisor Select 2 Communication Settings: 2 Word Select 1 3 Word Select 2 4 Word Select 3 Interrupt Control: 5 Transmit Control 1 6 Transmit Control 2 7 Receiver Interrupt Enable

20. 6850 : Configuration - Divisor An ACIA may be configured to suit a range of serial communications formats by setting the appropriate bits in the control register Clock divisor: Control Register bits CR1, CR0 CR0 Counter Divisor Select 1 CR1 Counter Divisor Select 2 CR1 CR0 Description 0 0 divide by 1 0 1 divide by 16 1 0 divide by 64 1 1 Master reset

21. 6850 : Configuration - Word Format Data word format Settings: CR2 Word Select 1 CR3 Word Select 2 CR4 Word Select 3 CR4 CR3 CR2 Description 0 0 0 7 data bits, 2 stop bits, even parity 0 0 1 7 data bits, 2 stop bits, odd parity 0 1 0 7 data bits, 1 stop bit, even parity 0 1 1 7 data bits, 1 stop bit, odd parity 1 0 0 8 data bits, 2 stop bits, no parity 1 0 1 8 data bits, 1 stop bit, no parity 1 1 0 8 data bits, 1 stop bit, even parity 1 1 1 8 data bits, 1 stop bit, odd parity

22. 6850 : Configuration - Interrupts Handshake and Interrupt Control: CR5 Transmit Control 1 CR6 Transmit Control 2 CR6 CR5 0 0 Set RTS = 0, Inhibit Transmit Interrupt 0 1 Set RTS = 0, Enable Transmit Interrupt 1 0 Set RTS = 1, Inhibit Transmit Interrupt 1 1 Set RTS = 0, Transmit “Break” and Inhibit Transmit Interrupt CR7 Receiver Interrupt Enable CR7 = 0 - Disable Interrupt in receive mode CR7 = 1 - Enable Interrupt in receive mode

23. HCCOM’s RS232 interface HCCOM uses Rockwell 6551 ACIA - similar to the M6850. The MAX238 converts from 0-5 volt signals to the +/- 10V signals required for RS232 standard. - Charge Pump.

24. Serial communications 16550 UART Configuration

25. Serial communications 16550 UART Configuration At IO Address COM1 3F8..3FF, COM2 2F8..2FF, COM3 3E8..3EF, COM4 2F8..2FF

27. Serial communications Interrupt Enable Register (IER) The IER enables each of the five types of interrupts and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarised in the previous table

28. Serial communications Interrupt Identification Register (IIR) P1 The ACE has an on-chip interrupt generation and prioritization capability. The ACE provides four prioritized levels of interrupts: Priority 1 - Receiver line status (highest priority) Priority 2 - Receiver data ready/receiver character time-out Priority 3 - Transmitter holding register empty Priority 4 - Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2).

29. Serial communications Interrupt Identification Register (IIR) P2 Detail on each bit is as follows: Bit 0: When bit 0 is cleared, an interrupt is pending Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in the previous table. Bit 3: This bit is always cleared in 16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending. Bits 4 and 5: not used (always cleared). Bits 6 and 7: These bits are always cleared in 16C450 mode. They are set when bit 0 of the FIFO control register is set.

30. Serial communications Line Control Register (LCR) In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. Bits 0 and 1: Number of bits in each serial character. 00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits Bit 2: Specifies either 1, 1.5 or 2 stop bits If Bit 3=: parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data parity is checked. If Bit 3=0: no parity is generated or checked.

31. Serial communications Line Control Register (LCR) When parity is enabled and: Bit 4=1 Even Parity - An even number of logic 1s in the data and parity bits is selected. Bit4=0 odd parity - An odd number of logic 1s is selected. Bit 5=1 Stick Parity. The parity bit set to 0. Bit 5=0 Stick parity is disabled.

32. Serial communications Line Control Register (LCR) Bit 6: Break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is forced to the spacing (cleared) state. Bit 7: Divisor Latch Access Bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.

33. Serial communications Line Status Register (LSR) Bit 0: Data Ready (DR) indicator for the receiver. DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO. Bit 1 : Overrun Error (OE) indicator. When OE is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register.

34. Serial communications Line Status Register (LSR) Bit 2: Parity Error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. Bit 3: Framing Error (FE) indicator. When FE is set, it indicates that the received character did not have a valid (set) stop bit. Bit 4: Break Interrupt (BI) indicator. When BI is set, it indicates that the received data input was held low for longer than a full-word transmission time.

35. Serial communications Line Status Register (LSR) Bit 5: Transmit Hold Register Empty (THRE) indicator. THRE is set when the THR is empty, indicating that the ACE is ready to transmit a new character. Bit 6: Transmitter Empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and shift register are both empty. Bit 7: Used In the FIFO mode to indicate an error condition in the FIFO buffer.

36. Serial communications Modem Control Register (MCR) Bit 0: This bit (DTR) controls the DTR output. Bit 1: This bit (RTS) controls the RTS output. Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal. Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal. Bit 5: AutoFlow Control Enable (AFE). When set, the autoflow control is enabled.

37. Serial communications Modem Control Register (MCR) Bit 4=1 Local Loop Back feature for diagnostic testing. The transmitter SOUT is set high. The receiver SIN is disconnected. The output of the TSR is looped back into the receiver shift register input. -The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. – The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs. – The four modem control outputs are forced to the inactive (high) levels.

38. Serial communications 16550 UART BAUD RATE Generation using a 3.072-MHz Crystal

39. Serial communications 16550 UART BAUD RATE Generation using a 1.8432 MHz Crystal

40. Establishing A Comms Link

41. Serial communications

42. Serial communications

43. Modern Serial communications The 16C550x are functional upgrades of the of the 16C450 - equivalent to the 16C450 on power up, but can be placed in an alternate FIFO mode. The automatic FIFO mode relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

44. Modern Serial communications In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS input signals.

45. Automatic Flow Control ACE - Asynchronous Communications Element ACIA - Asynchronous Communications Interface Adapter UART - Universal Asyncronous Receiver Transmitter

46. RS232 Cables DTE (Data Terminal Equipment eg: Computers & Terminals) DTE Pin Descriptions:

47. RS232 Cables DCE to DTE Straight Through Computer to Modem Cable

48. RS232 Cables Popular Wiring Methods for RS232 DTE to DTE “Null Modem” - Eg “Laplink”

49. RS232 Cables DTE to DTE “3-Wire Null Modem” Serial Terminal to Computer Cable. Requires XON-XOFF flow control

50. RS232 Cables 9 Pin to 25 Pin Connector DTE-DTE cable