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CSC Trigger at SLHC

CSC Trigger at SLHC. Chamber issues General front-end electronics issues Trigger-specific issues. General CSC Issues I. (Aside: Barrel, with its long drift times, may not be able to survive (??), what would replace it?)

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CSC Trigger at SLHC

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  1. CSC Trigger at SLHC • Chamber issues • General front-end electronics issues • Trigger-specific issues

  2. General CSC Issues I • (Aside: Barrel, with its long drift times, may not be able to survive (??), what would replace it?) • A rear shielding wall is needed for ME4/2 and 10^34 or higher luminosity. • Additional simulation studies of shielding near collimators and magnets should be done. • Aging tests have not been done for ME1/1 chambers(!) • Need to redo aging tests for other chambers for SLHC anyway. Long time exposures needed at GIF (~1 year).

  3. General CSC Issues II • Will we bring muon tracks into coincidence with a track trigger? • A track coincidence should identify the crossing and make a Pt cut sharper. • It might be necessary to add a track isolation requirement to a track coincidence, since a sharper Pt cut may not be enough to bring down rate sufficiently.

  4. CSC electronics have been shown to be capable of functioning with high muon track rates with slight tweaking to CLCT (see below). High neutron background hit rates may be a different matter. Chamber #1 CLCT 2,000 1,500 CLCT Rate (KHz) 1,000 data consistent with dead-time = 225 ns 500 0 0 500 1,000 1,500 2,000 2,500 3,000 Beam Intensity (KHz) Front-End Electronics Issues I SLHC (10xLHC) SLHC SLHC (10xLHC) SLHC Max. LHC Max. LHC

  5. Probably no problem with radiation damage to present CFEB and ALCT components, given tests at Davis cyclotron and Ohio State. Anode occupancy at SLHC will be a few %. Cathode occupancy is more like 20% (Andrey's estimate) since shaping time is longer and clusters occupy multiple strips. No existing studies of offline cathode position resolution for high neutron rates (is that true?) SCA pipeline length looks like potential problem for CFEBs, since 10x as many tracks means using 10x as many buffers, and SCA buffers are limited. Also, if L1 latency changes much, that is a problem for SCA buffers. New CFEBs: replace SCAs and ADCs by flash ADCs on each channel and digital memory? Front-End Electronics Issues II

  6. CSC Trigger Issues I • If CFEBs use flash ADCs, then trigger comparator ASICs could be replaced with something more precise. • Log[qn/(qn+qn+1)] is thought to be almost linear with position. • Trigger position to 1mm would give better rejection of neutron background. • It might be interesting to form CLCTs on the chambers themselves (is there any space available on chambers for another board?).

  7. CSC Trigger Issues II • Basic notion for trigger: currently ~5 cathode hits/chamber in any random time slice, at maximum LHC luminosity, that will grow to ~50 hits. Can anticipate needing much tighter LCT cuts. • Trigger position to 1mm would give better rejection of neutron background. • It looks attractive to replace TMB and ALCT mezzanine card FPGAs: • Current ones will be 10 year-old technology. • Improved algorithms will be needed to deal with very large number of background neutron hits. • (x25?) Faster speed required if no extra latency allowed for track coincidence • current ALCTs require frequent resets due to SEU's.

  8. CSC Trigger Issues III • Bunch crossing ID: CSC’s themselves cannot uniquely identify a 12.5ns bunch crossing due to intrinsic drift time. • Silicon track trigger could do the job. CSC/Si track coincidence could be made at Global Muon Trigger. • Otherwise, RPC coincidence in 1st station might work if RPC occupancy low enough and RPCs reliable enough. • Will there be an RPC replacement, e.g. scintillator?

  9. CSC Trigger Issues IV • For Tridas, MPCs should probably be replaced. Bottleneck of 3 muons per sector will be important limitation, and optical link technology will be much advanced by then.

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