Memristor Memory With Crossbar Architecture

1. Memristor Memory With Crossbar Architecture Naveen Murlimanohar HP Labs June 14th 2014

2. Why New Technology? • Explosion of data – faster than Moore’s law • Memory is the focal point • Strong demand for cheap memory • In memory computation is gaining popularity • Volt DB, SAP HANA, Memcached • DRAM cost/bit is high and its scaling is slowing • DRAM is also volatile • Other technologies such as PCM and STT-RAM are facing challenges

3. Technology Trend – Memory Scaling Problem • DRAM capacity increase 4X / 3years for decades, but now is scaling much slower Source: Horst Simon

4. Memory Capacity Ref: DARPA’s exascale report • Requirement  1B/FLOP • By 2020 we could be well below <0.1B/FLOP! • More number crunching with less data

5. Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities

6. MEMRISTOR dφ = M dq 1971 Chua The memristor: 4th fundamental two terminal circuit element Reduced to practice 2008 R. Stanley WilliamsHP Laboratories v Predicted 1971 Leon Chua U.C. Berkeley Ohm 1827 Von Kleist 1745 RESISTOR dv = R di CAPACITOR dq = C dv q i INDUCTOR dφ = L di 1831 Faraday φ

7. Memristor - First Glance • The memristor is built on a Metal-Insulator-Metal (MIM) structure. • Memristor can be switched between High Resistance State (HRS) and Low Resistance State (LRS) by applying an external voltage across the cell. • Current, voltage relationship is non-linear HP Confidential

8. Memristor Cell Ideally we want the memristor IV curve to be highly non-linear Selector with high non-linearity Memristor Cell Memristor switching device with low non-linearity Combination of a selector in series with memristor device HP Confidential Memristor Selector

9. Accessing Traditional Memory • 2D grid of cells with a dedicated access switch in each cell • Easier to read/write to a cell • Low density but high read margin HP Confidential

10. Traditional Memory vs. Memristor Crossbar Row select signal to read or write a row Cells being read or written HP Confidential

11. Traditional Memory vs. Memristor Crossbar Access transistor isolates unnecessary signal - But it increases cost Cells being read or written HP Confidential

12. Crossbar Memristor array Half Selected Cell Selected Cell • No access transistor  a dense crossbar array with a cell size of 4F2 • You can lay transistors and circuits below the array • Maximum use of silicon area HP Confidential

13. Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities

14. Memristor Operation Row select signal to read or write a row Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 0 Vdd/2 Vdd/2 Vdd/2 Vdd Vdd/2 Vdd/2 Vdd/2 HP Confidential

15. Memristor Operation Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 0 Vdd/2 Vdd/2 Vdd/2 Vdd Half Selected Cells Leak Current Vdd/2 Vdd/2 Vdd/2 Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2) HP Confidential

16. Memristor Operation Unselected cells shown in light blue will also get impacted Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 0 Vdd/2 Vdd/2 Vdd/2 Vdd Vdd/2 Vdd/2 Vdd/2 Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2) HP Confidential

17. Complex Tradeoffs in Crossbar Write Enough voltage drop (for switching) Avoid write disturbance Array size I? V selected cell Read V/2? V/3? Floating? >1 bit? ? Enough ∆I (noise margin) HP Confidential

18. Complex Tradeoffs in Designing Memristor Crossbar Enough voltage drop (for switching) Avoid write disturbance • Design decisions are not obvious • What is the optimal array dimensions? • What is the right driving voltage? • What is the biasing voltage? • Tradeoff in writing/reading single bit vs. multiple bits per array I? V selected cell V/2? V/3? Floating? ? Enough ∆I (noise margin) Depending upon the delay/energy/area constraints, we can tune the array accordingly HP Confidential

19. Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities

20. Operating Voltage vs. Array Size • Big array requires large voltage HP Confidential

21. Choice of Material • Non-linearity (Kr) helps reduce leakage current Kr = ILSR(@VSET) / ILSR(@VSET/2) Maximum Number of Wordlines & Bitlines • Non-linearity increases the density HP Confidential

22. Read Operation • The read voltage/current is lower than that of the write operation • The read reliability is determined by the voltage swing for reading HRS and LRS cells • However, sneak path and data pattern can reduce the voltage swing

23. Operating Speed vs. Density vs. Bandwidth • Larger array  More sneak paths  Lower read margin • Challenging with process variation HP Confidential

24. Two-Step Read Operation • Two-step sensing: senses the background current first, then the overall current is sensed • Increased sensing overhead  low bandwidth or poor density One-step Reading Two-step Reading HP Confidential

25. Outline • Need for a new technology • Why Memristor is different? • Crossbar Architecture • Tradeoffs in Crossbar Architecture • Opportunities

26. More Challenges • Reliability of crossbar • Process variation • Fault tolerance • Data encoding

27. Effect of Data on Sneak Current Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 0 Vdd/2 Vdd/2 Vdd/2 Vdd Half Selected Cells Leak Current 0 1 0 0 0 1 Cells in low resistance state  More sneak current HP Confidential

28. Impact of data pattern • Write the furthest cell in a 8x8 cross-point array • # of “1”s (LRS) in the selected wordline matters • gap between worst-case and best case? HP Confidential

29. Impact of data pattern • Write the furthest cell in a 8x8 cross-point array • positions of “1”s (LRS) in the selected wordline also matter • moving “1”s closer to the write driver helps • hints: mirror coding HP Confidential

30. Summary • Opportunity to change the memory technology do not come along everyday • More aggressive micro architecture that can provide better density than existing technologies is critical • Memristor characteristics are well suited for future memory systems • Crossbar architecture is an interesting way to leverage resistive memories such as Memristor • Its high density along with architectural enhancements can make it a compelling option for future systems HP Confidential

31. Memristor . . . More Info . . . Resources – Learn more… • Memristor Basic Info: • The Memristor – Incredible: https://www.youtube.com/watch?v=wZAHG3COYYA • Wikipedia on Memristor: http://en.wikipedia.org/wiki/Memristor • Technical papers: • Niu et al., Design of Cross-point Metal-oxide ReRAM Emphasizing Reliability and Cost.", (ICCAD), 2013. • Xu et al., Understanding the Tradeoffs in MLC ReRAM Memory Design, DAC, 2013. • Niu et al., Design Tradeoffs for High Density Cross-Point Resistive Memory.", ISLPED, 2012.

32. The basic model of crossbar array Voltage controlled current source Current controlled voltage source • Vw/ V’w : Voltage at the edge of wordline • VB / V’B : Voltage at the edge of bitline • Rl : Interconnection wire resistance • Ri,j : Resistance of the memristor at the intersection of the ithwordline and the jth bitline • Vi,j / V’i,j : Top/bottom voltage of the memristor with Ri,j • Array simulation is done through HSPICE Memristor Selector