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SOI BiCMOS  an Emerging Mixed-Signal Technology Platform

SOI BiCMOS  an Emerging Mixed-Signal Technology Platform. Tak H. Ning. Outline. Evolution of Silicon Technology CMOS for Mixed Signal -- Why and Why Not? Why SOI BiCMOS for Mixed Signal? Some Recent Developments Summary. Evolution of Silicon Technology. CMOS + ?. CMOS. BiCMOS.

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SOI BiCMOS  an Emerging Mixed-Signal Technology Platform

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  1. SOI BiCMOS an Emerging Mixed-Signal Technology Platform Tak H. Ning

  2. Outline • Evolution of Silicon Technology • CMOS for Mixed Signal -- Why and Why Not? • Why SOI BiCMOS for Mixed Signal? • Some Recent Developments • Summary

  3. Evolution of Silicon Technology CMOS + ? CMOS BiCMOS PMOS/NMOS BIPOLAR 1960 1980 1950 1970 2000 1990 CMOS First invented bipolar First transistor (1963) MOSFET (1947) (1960)

  4. What Happened to BiCMOS? • Previous BiCMOS aimed primarily for digital applications • CMOS was low power but very slow • Digital BiCMOS goal was to add bipolar to speed up CMOS circuits • PENTIUM 1 was BiCMOS! • CMOS speed improved by scaling • Need for digital BiCMOS disappeared by early 1990’s

  5. Devices Capable of e-Commerce Worldwide Technology required: computing + communication

  6. High-Speed CMOS Trends • Power supply voltage ~ 1 V • Gate oxide thickness ~ 1 nm • Short channel length but high off current • Not suitable for many analog applications gate Gate oxide source drain Channel length

  7. Technology Drivers and Trends • System needs • Faster, smaller, lower power, more reliable • It is a mixed-signal world! • CMOS for computing • For communication : • RF and analog CMOS, if it can be done • Silicon bipolar, if CMOS cannot do it • Non-silicon only if unavoidable

  8. Analog Transistors Typical MOSFET Typical bipolar Bipolar is preferred

  9. Why BiCMOS? • Systems need • CMOS for high density and low power digital functions • Bipolar for RF and analog functions • Integration for better systems • Faster, smaller, lower power, more reliable • Status: • ALL major semiconductor companies either shipping or developing BiCMOS

  10. Why Not BiCMOS? • Cost, Cost, and Cost • Process complexity • Need to evaluate cost versus benefit • Circuit design challenges: • CMOS voltages scale (up to a point) • Bipolar voltages do not scale

  11. Why SOI BiCMOS? • SOI CMOS is here; bipolar is needed • Isolation • Devices automatically isolated from one another • Reduced substrate-coupling noise • Cost? • SOI wafer cost adder • Cost saving associated with isolation • Opportunities for innovation

  12. Why SiGe-Base Bipolar? SiGe-base • A much better RF and analog transistor • Higher current gain • Larger Early voltage • Smaller transit times E B C n+ p+ p+ n n+ n+ subcollector

  13. Improvement Factor: (SiGe)/(Si)

  14. The Challenge of BiCMOS Bipolar MOSFET • Buried layer thickness issue • Isolation issue G E B C n+ p+ p+ S D n n+ ~ 0.2 mm n+ subcollector ~ 2 mm

  15. The Challenge of SOI BiCMOS Bipolar SOI CMOS Buried oxide subcollector

  16. SOI BiCMOS SOI BiCMOS has been around for years! What’s new?

  17. SOI BiCMOS -- for Mainframes • SOI for reducing soft-error rate • No power/speed advantage for CMOS Source: Hitachi, 1992 IEDM

  18. SOI BiCMOS -- for Mixed Signal • SOI on high-resistivity substrate • 1 mm Si; no SOI advantage for CMOS Source: Hitachi, IEEE TED, vol. 49, 2002

  19. Bipolar Transistors: from Bulk to Thin SOI E E B C B n+ C n+ p+ p+ p+ n n+ 0.1mm n n+ n+ n+ subcollector buried oxide substrate of SOI ~ 2 mm Bulk Thin SOI • Fully depleted collector SOI bipolar

  20. Fully-Depleted-Collector SOI Bipolar • Electrons drift across depleted collector • region towards reachthrough Source: J. Cai et al., 2002 Symp. VLSI Technology

  21. SOI Vs. Bulk SiGe Bipolar Device C E B Subcollector Experiment SOI bipolar IBM’s Production SiGe Bipolar

  22. Measured I-V Characteristics

  23. Measured Cutoff Frequency

  24. What About Cost? • Cost adder: • SOI substrate • Cost subtracters: • No subcollector • No epi • No deep trench • Must look at cost versus benefit

  25. Complementary BiCMOS PNP PMOS NMOS INDUCTOR NPN • No SOI • fT of npn = 25 GHz • fT of pnp = 2.5 GHz Source: NEC, 1998 IEDM

  26. SOI Complementary BiCMOS pnp npn nMOS pMOS E E G G B B p+ n+ C C S D D S p+ n+ p+ n+ n+ n+ n+ p+ p+ p n p+ p+ n+ n+ p n buried oxide substrate of SOI • npn, pnp, and CMOS on same thin SOI

  27. Advantage of Complementary Bipolar Source: Hitachi, IEEE TED, 1995

  28. Summary Mixed-Signal Technology Performance SOI BiCMOS CMOS Time

  29. Summary • Silicon technology evolution continues at rapid pace • CMOS development is rapidly reaching its limits • Opportunities around the corner of the redbrick wall • SOI BiCMOS likely to emerge as preferred technology platform for mixed-signal applications

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