Lessons Learned The Hard Way: FPGA  PCB Integration Challenges

1. Lessons Learned The Hard Way: FPGA  PCB Integration Challenges Dave Brady & Bruce Riggins

2. Agenda • Design Overview • Design Challenge Summary • Lessons Learned • Suggested Strategies

3. System Design Challenges • Complex system implemented using multiple high-pin count FPGAs • PCB bus speeds > 150 Mhz • PCB physical size restricted • Implementation team (s) • System design, 2 engineers • System architecture, Embedded CPU h/w design • PCB design, 1 engineer • Functional design, PCB timing, PCB signal integrity • PCB physical design, 1 engineer • PCB place and route, design for manufacturing • FPGA design, 5 engineers • RTL HDL development • DSP design, 1 engineer • C algorithm development • Embedded software development, 2 engineers

4. Conceptual Design Overview PCB DRAMMemoryModules FPGA Boot Module FPGA 1 CPU & Embedded Platform Glue Logic Custom (ASIC) Logic Voltage Regulators/Generators FPGA 2 Clock Generators Custom (ASIC) Logic DSP Glue Logic Communication Module Communication Module

5. Design Challenge Summary • Overdriven signals • Cross talk • Simultaneous switching outputs • Meeting system performance specifications • Minimizing PCB manufacturing costs • Learning the FPGA device-specific I/O design rules • Maintaining (updating) FPGA symbols for the PCB schematic • Leveraging the complete design team

6. Lessons Learned: Increasing PCB CostsStarted with FPGA Timing • FPGA 1 pin-to-pin timing exceeded spec by 100 ps • FPGA designer increased drive strength • Pin-to-pin timing meets spec PCB FPGA 1 FPGA 2 Tp > Spec by 100 ps

7. Increasing PCB CostsInduced Signal Ringing on PCB (contd.) • Increasing drive strength on FPGA 1 output pin induced PCB signal ringing • PCB engineer identified PCB FPGA 1 FPGA 2 Tp < Spec

8. Increasing PCB CostsInduced Signal Ringing on PCB (contd.) • PCB engineer began inserting termination networks • Results: •  PCB component count •  PCB via count •  PCB trace count •  PCB routability •  PCB costs PCB R FPGA 1 FPGA 2 Tp < Spec

9. Lessons Learned: Increasing PCB Costs --Scoping the Problem • Not an issue for a single trace • Design contained four 64-bit high-speed data busses • All 256 signals were impacted! PCB B1data(0:63) FPGA 1 FPGA 2 B2data(0:63) B3data(0:63) Tp < Spec B4data(0:63)

10. Lessons Learned: Big Busses  Cross Talk • Busses laid out on PCB with matching trace (tp) lengths • Identified by the PCB engineer • Traditional solutions: • Increase trace-to-trace separation • Leverage lower-dielectric PCB laminates PCB B1data(0) FPGA 1 FPGA 2 B1data(1) B1data(2) Tp < Spec B1data(63)

11. Lessons Learned: Big Busses  Simultaneous Switching Outputs • Grouping busses into the same pin bank improves PCB routability • FPGA pin banks are limited in the current they may source • Leads to SSO issues PCB B1data(0:63) FPGA 1 FPGA 2 B2data(0:63) B3data(0:63) Tp < Spec B4data(0:63)

12. Balance is the Key FPGA I/O Drive Strength Setting Signal Too Slow Signal Ringing FPGA I/O Rail Voltage Setting Simultaneous Switching Output Issues Signal Cross Talk

13. TPD=Pass TPD=Pass TPD=Fail Lessons Learned: Leveraging I/O Flexibility • Both FPGA devices designed to specs • Unable to meet system timing specs

14. TPD=Pass TPD=Fail TPD=Fail Leveraging I/O Flexibility (contd.) • Changed the physical location of signals on the FPGA • Unable to meet timing in one FPGA

15. TPD=Pass TPD=Pass TPD=Pass Leveraging I/O Flexibility (contd.) • Changed the physical location of signals (again) • Finally met system timing specs • Simple for a single signal  Complex for wide busses

16. Lessons Learned: The Domino Effect of Pin Swapping 3 1 2

17. Pin Bank PROG_B 3GIO Single Ended Clock Double Ended M1 CCLK M2 M0 DONE All Pins Are Not The Same

18. Virtex II Pro: Input AC Characteristics Source: Xilinx website

19. Virtex II Pro: Input AC Characteristics Source: Xilinx website

20. Virtex II Pro: Input AC Characteristics Source: Xilinx website

21. 1500 Pin device 560 Pin device 100 Pin device Resolving Symbol Size

22. Synchronizing the FPGA & PCB Flows Physical Placement & Connectivity

23. Multiple Perspectives That Don’t Match FPGA and PCB design teams typically do not communicate

24. Suggested Strategies: Eliminate Team Communication Barriers We do the FPGA I/O Design System Designer PCB (Schematic) Designer We do the FPGA I/O Design We do the FPGA I/O Design FPGA Designer Embedded System (CPU) Designer PCB Layout We do the FPGA I/O Design We do the FPGA I/O Design We do the FPGA I/O Design PCB Timing Analysis DSP Designer We do the FPGA I/O Design PCB Signal Integrity We do the FPGA I/O Design

25. General Tips & Tricks • Leverage Signal Integrity “What if” Analysis Early • Anticipate signal ringing, cross talk, ground bounce, etc. • Develop system constraints to minimize PCB components • Make trade-offs at the system level • Run Signal Integrity Analysis on the PCB Design • Interactive part of the normal design process • NOT a design verification “check box” • Leverage Embedded Resistors • Some signal termination is un-avoidable • Minimize PCB size • Reduced PCB costs • Leveraging Gigabit Transceivers Reduces PCB Traces BUT • GHz signals  High-Speed (& cost) PCB laminates • Introduces additional PCB components (clock generators, voltage regulators, etc) • Introduces additional termination topology requirements • Re-partition the FPGA Design to Optimize PCB Performance • Alternative to leveraging Gigabit transceivers • Will not work for every design • Worked for this design

26. Routing Comparison • Routing after I/O Designer optimization • 49% length reduction (320 ps less delay) • Reduced routing congestion and excess

27. FPGA 1 FPGA 2 Optimized IO PCB PCB Layer Reduction

28. Pin-out changes Pin-out changes Pin-out changes Pin-out assign PCB design Reduce Overall System Design Time • Concurrent design of FPGA and PCB • Optimize system performance & reduce manufacturing costs • Solution: Bi-directional FPGA I/O design FPGA design • I/O Designer • Reduced Design Time • Enhanced System Integration • Optimized Performance • Lowered Manufacturing Costs PCB design

29. Provide PCB Designers an Intelligent FPGA I/O Design Tool

30. Show FPGA Designers the PCB Design

31. Provide Everyone Detailed Control

32. Automate Pin Planning • Routing after I/O Designer optimization • 49% length reduction (320 ps less delay) • Reduced routing congestion and excess

33. 100Mhz Clock FPGA 1 FPGA 2 Optimized IO PCB I/O Design Planning Benefits Output to Setup = Pass Clock to Output = Pass • Meet performance constraints • Overall timing constraints • FPGA in-chip • On board • PCB signal integrity constraints • Comply with FPGA technology I/O rules • Eliminate PCB signal layers Board Interconnect Budget = FAIL

34. The Complete Flow Including PCB Physical Design • Flow Integration • Schematic to layout • Layout to I/O pin planning • FPGA Designer has visibility into the PCB design • PCB designer has access to I/O design rules • Fast pin swaps • Automatic bus untangling