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332:479 Concepts in VLSI Design Lecture 13 Sequential Circuits

332:479 Concepts in VLSI Design Lecture 13 Sequential Circuits. David Harris and Mike Bushnell Harvey Mudd College and Rutgers University Spring 2004. Outline. Floorplanning Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Two-Phase Clocking Summary.

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332:479 Concepts in VLSI Design Lecture 13 Sequential Circuits

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  1. 332:479 Concepts in VLSIDesignLecture 13 Sequential Circuits David Harris and Mike Bushnell Harvey Mudd College and Rutgers University Spring 2004

  2. Outline • Floorplanning • Sequencing • Sequencing Element Design • Max and Min-Delay • Clock Skew • Two-Phase Clocking • Summary Material from: CMOS VLSI Design By Neil E. Weste and David Harris Concepts in VLSI Des. Lec. 13

  3. Project Strategy • Proposal • Specifies inputs, outputs, relation between them • Floorplan • Begins with block diagram • Annotate dimensions and location of each block • Requires detailed paper design • Schematic • Make paper design simulate correctly • Layout • Physical design, DRC, NCC, ERC Concepts in VLSI Des. Lec. 13

  4. Floorplan • How do you estimate block areas? • Begin with block diagram • Each block has • Inputs • Outputs • Function (draw schematic) • Type: array, datapath, random logic • Estimation depends on type of logic Concepts in VLSI Des. Lec. 13

  5. MIPS Floorplan Concepts in VLSI Des. Lec. 13

  6. Area Estimation • Arrays: • Layout basic cell • Calculate core area from # of cells • Allow area for decoders, column circuitry • Datapaths • Sketch slice plan • Count area of cells from cell library • Ensure wiring is possible • Random logic • Compare complexity do a design you have done Concepts in VLSI Des. Lec. 13

  7. MIPS Slice Plan Concepts in VLSI Des. Lec. 13

  8. Typical Layout Densities • Typical numbers of high-quality layout • Derate by 2 for class projects to allow routing and some sloppy layout. • Allocate space for big wiring channels Concepts in VLSI Des. Lec. 13

  9. Sequencing • Combinational logic (CL) • output depends on current inputs • Sequential logic • output depends on current and previous inputs • Requires separating previous, current, future • Called state or tokens • Ex: FSM, pipeline Concepts in VLSI Des. Lec. 13

  10. Pipelined System • Huffman Model Finite State Machine (FSM) & pipelined system Concepts in VLSI Des. Lec. 13

  11. Sequencing (cont’d.) • If tokens moved through pipeline at constant speed, no sequencing elements would be necessary • Ex: fiber-optic cable • Light pulses (tokens) are sent down cable • Next pulse sent before first reaches end of cable • No need for hardware to separate pulses • But dispersion sets min. time between pulses • This is called wave pipelining in circuits • In most circuits, dispersion is high • Delay fast tokens so they don’t catch slow ones. Concepts in VLSI Des. Lec. 13

  12. Sequencing Overhead • Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. • Inevitably adds some delay to the slow tokens • Makes circuit slower than just the logic delay • Called sequencing overhead • Some people call this clocking overhead • But it applies to asynchronous circuits too • Inevitable side effect of maintaining sequence Concepts in VLSI Des. Lec. 13

  13. Sequencing Elements • Latch: Level sensitive • a.k.a. transparent latch, D latch • Flip-flop: edge triggered • A.k.a. master-slave flip-flop, D flip-flop, D register • Timing Diagrams • Transparent • Opaque • Edge-trigger Concepts in VLSI Des. Lec. 13

  14. Sequencing Elements • Latch: Level sensitive • a.k.a. transparent latch, D latch • Flip-flop: edge triggered • A.k.a. master-slave flip-flop, D flip-flop, D register • Timing Diagrams • Transparent • Opaque • Edge-trigger Concepts in VLSI Des. Lec. 13

  15. Latch Design • Pass Transistor Latch • Pros + + • Cons Concepts in VLSI Des. Lec. 13

  16. Latch Design • Pass Transistor Latch • Pros + Tiny + Low clock load • Cons • Vt drop • nonrestoring • backdriving • output noise sensitivity • dynamic • diffusion input Used in 1970’s Concepts in VLSI Des. Lec. 13

  17. Latch Design • Transmission gate + - Concepts in VLSI Des. Lec. 13

  18. Latch Design • Transmission gate + No Vt drop - Requires inverted clock Concepts in VLSI Des. Lec. 13

  19. Latch Design • Inverting buffer + + + Fixes either Concepts in VLSI Des. Lec. 13

  20. Latch Design • Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input • Inverted output Concepts in VLSI Des. Lec. 13

  21. Latch Design • Tristate feedback + Concepts in VLSI Des. Lec. 13

  22. Latch Design • Tristate feedback + Static • Backdriving risk • Static latches are now essential Concepts in VLSI Des. Lec. 13

  23. Latch Design • Buffered input + + Concepts in VLSI Des. Lec. 13

  24. Latch Design • Buffered input + Fixes diffusion input + Noninverting Concepts in VLSI Des. Lec. 13

  25. Latch Design • Buffered output + Concepts in VLSI Des. Lec. 13

  26. Latch Design • Buffered output + No backdriving • Widely used in standard cells + Very robust (most important) • Rather large • Rather slow (1.5 – 2 FO4 delays) • High clock loading Concepts in VLSI Des. Lec. 13

  27. Latch Design • Datapath latch + - Concepts in VLSI Des. Lec. 13

  28. Latch Design • Datapath latch + Smaller, faster - Unbuffered input Concepts in VLSI Des. Lec. 13

  29. Flip-Flop Design • Flip-flop is built as pair of back-to-back latches Concepts in VLSI Des. Lec. 13

  30. Enable • Enable: ignore clock when en = 0 • Mux: increase latch D-Q delay • Clock Gating: increase en setup time, skew Concepts in VLSI Des. Lec. 13

  31. Reset • Force output low when reset asserted • Synchronous vs. asynchronous Concepts in VLSI Des. Lec. 13

  32. Set / Reset • Set forces output high when enabled • Flip-flop with asynchronous set and reset Concepts in VLSI Des. Lec. 13

  33. Positive Edge Triggering Concepts in VLSI Des. Lec. 13

  34. Negative and Positive Latches Concepts in VLSI Des. Lec. 13

  35. Positive Edge-Triggered Reg. Concepts in VLSI Des. Lec. 13

  36. T Flip-Flop Concepts in VLSI Des. Lec. 13

  37. JK Flip-FLop Concepts in VLSI Des. Lec. 13

  38. Sequencing Methods • Flip-flops • 2-Phase Latches • Pulsed Latches Concepts in VLSI Des. Lec. 13

  39. Timing Diagrams Contamination and Propagation Delays Concepts in VLSI Des. Lec. 13

  40. Max-Delay: Flip-Flops Concepts in VLSI Des. Lec. 13

  41. Max-Delay: Flip-Flops Concepts in VLSI Des. Lec. 13

  42. Max Delay: 2-Phase Latches Concepts in VLSI Des. Lec. 13

  43. Max Delay: 2-Phase Latches Concepts in VLSI Des. Lec. 13

  44. Max Delay: Pulsed Latches Concepts in VLSI Des. Lec. 13

  45. Max Delay: Pulsed Latches Concepts in VLSI Des. Lec. 13

  46. Min-Delay: Flip-Flops Concepts in VLSI Des. Lec. 13

  47. Min-Delay: Flip-Flops Concepts in VLSI Des. Lec. 13

  48. Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Concepts in VLSI Des. Lec. 13

  49. Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Concepts in VLSI Des. Lec. 13

  50. Min-Delay: Pulsed Latches Hold time increased by pulse width Concepts in VLSI Des. Lec. 13

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