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Lecture 8 Sequential Logic

CS147. Lecture 8 Sequential Logic. Prof. Sin-Min Lee Department of Computer Science. Implement D Flip-flop by T Flip-flop. Q. Q. 0 1. 0 1. D. T. 0 1. 0 1. 0 1. 0 0. 1 0. 1 1. T = D Q’ + D’ Q

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Lecture 8 Sequential Logic

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  1. CS147 Lecture 8 Sequential Logic Prof. Sin-Min Lee Department of Computer Science

  2. Implement D Flip-flop by T Flip-flop Q Q 0 1 0 1 D T 0 1 0 1 0 1 0 0 1 0 1 1 T = D Q’ + D’ Q D D’ T

  3. Implement JK Flip-flop by D Flip-flop Q Q 0 1 0 1 J K J K D Q+ 0 0 0 1 1 1 1 0 • 0 1 • 0 0 • 0 • 1 1 0 0 0 1 1 1 1 0 • 0 1 • 0 0 • 0 • 1 1 0 1 0 1 D = J Q’ + K’ Q Q J D K Q’

  4. Implement JK Flip-flop by T Flip-flop Q+ Q Q 0 1 0 1 J K Q+ J K J K T Q+ 0 0 0 1 1 1 1 0 • 0 1 • 0 0 • 0 • 1 1 0 0 0 1 1 1 1 0 • 0 0 • 0 1 • 1 • 1 0 0 0 0 1 1 0 1 1 Q 0 1 Q’ Q Q’ 0 1 T = J Q’ + K Q Q J T K Q’

  5. Implement T Flip-flop by JK Flip-flop Q T 0 1 J K Q Q+ 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 X 1 X X 1 X 0 Q Q T 0 1 T 0 1 X 0 X 1 0 X 1 X 0 1 0 1 K = T J = T

  6. Random-Access Memory • Can read and write at any point in memory • Implemented using D Flip-Flops • Each row contains 16 Flip-Flops • A Decoder

  7. Binary Counter • Holds each pulse in memory • Each pulse add another number • Binary format

  8. Register • Used to hold one item of information • CPU’s have many registers • AX is an example in Assembly

  9. Clocks and Sequencers • To perform operations a CPU often requires a specific sequence of sub operations • A sequencer is used to make sure operations happen in correct order • A clock is a circuit that outputs 0’s and 1’s at specific frequencies

  10. Real World Application • The RAM discussed is a model for a chip that can actually be found in a computer • The binary counter can be bought at http://www.web-tronics.com/webtronics/74hc161n.html for 45 cents each • The Flip-Flop circuits are models of usable chips

  11. State Diagrams • A state diagram: • Each state is represented by a circled vertex • Each row of the state table is shown as directed arc J’ Y

  12. Important Rule for State Diagram • State diagram has same situation as state table. Their conditions should be mutually exclusive, no input values should meet the condition of more than one arc.

  13. The Alarm Clock Presentstate Turn off alarm Alarm Weekday Nextstate On X Awake in bed Asleep Yes Awake in bed Off Yes No Awake and up No Awake in bed Asleep No Off

  14. State Diagram for The Alarm Clock (a) Alarm Turn off Alarm = Yes Asleep Awake in bed Alarm’ Alarm Alarm’ /\ Weekday Alarm’ /\ Weekday’ Awake and up 1 (Always) ( a )

  15. The alarm clock problem with inactionstates Present state Alarm Weekday Next state Turn off alarm Asleep Asleep Off X No On X Yes Asleep Awake in bed Awake in bed X yes On Awake in bed Off Yes Awake and up No Awake in bed Awake in bed Off No Asleep No X Awake and up X Awake and up No

  16. State Diagram for The Alarm Clock (b) Alarm / 1 Asleep Awake in bed Alarm’ / 0 Alarm / 1 Alarm’ /\ Weekday / 0 Alarm’ /\ Weekday’ / 0 Awake and up 1 (Always) / 0 ( b ) 1 = yes turn off alarm (output) 0 – no turn off alarm (output)

  17. State Tables for The JK Flip-Flop Present State J K Next State Q Y 0 0 Y 0 Y 0 1 Y 0 Y 1 0 Z 1 Y 1 1 Z 1 Z 0 0 Z 1 Z 0 1 Y 0 Z 1 0 Z 1 Z 1 1 Y 0 ( a )

  18. Condition in Terms of J and K J J’ K’ Z Y Q=0 Q=1 K

  19. Mealy and Moore Machines • A finite state machine can represent outputs in one of two ways • Moore Machines • Mealy Machines

  20. Moore Machines • Moore Machines • Associates its outputs with the states. • Output values depend only on the state and not on the transitions. • It requires less hardware to produce the output values • It is well suited for representing the control units of microprocessors and cpu.

  21. State Diagram for The Alarm Clock (a) Alarm Turn off Alarm = Yes Asleep Awake in bed Alarm’ Alarm Alarm’ /\ Weekday Alarm’ /\ Weekday’ Awake and up 1 (Always) Moore Machine

  22. Mealy Machines • Mealy Machines • Associates outputs with the transitions. • It depends on both its state and its input values

  23. State Diagram for The Alarm Clock (b) Alarm / 1 Asleep Awake in bed Alarm’ / 0 Alarm / 1 Alarm’ /\ Weekday / 0 Alarm’ /\ Weekday’ / 0 Awake and up 1 (Always) / 0 Mealy Machine

  24. Designing State Diagrams • Counter • String Checker • Toll Booth

  25. Modulo 6 Counter • A modulo 6 counter is a 3-bit counter that counts through the sequence. • 000 001 010 011 100 101 000… • 0 1 2 3 4 5 0 … Unlike a regular 3-bit counter 110(6) and 111(7) do not count

  26. State Table for The Modulo 6 Counter Present State U Next State C V2 V1 V0 S0 0 S0 1 0 0 0 S0 1 S1 0 0 0 1 S1 0 S1 0 0 0 1 S1 1 S2 0 0 1 0 S2 0 S2 0 0 1 0 S2 1 S3 0 0 1 1 S3 0 S3 0 0 1 1 S3 0 1 0 0 1 S4 S4 0 S4 0 1 0 0 S4 1 S5 0 1 0 1 S5 0 S5 0 1 0 1 S5 1 S0 1 0 0 0

  27. State Diagram for The Modulo 6 Counter (Mealy) 0 / 1000 0 / 0001 0 / 0010 S0 S1 S2 1 / 0001 1 / 0010 1 / 1000 1 / 0011 S5 S4 S3 1 / 0101 1 / 0100 0 / 0101 0 / 0100 0 / 0011 ( a ) Mealy

  28. State Diagram for The Modulo 6 Counter (Moore) C=0 V=0010 C=1 V =000 C=0 V=010 S0 S1 U U S2 U’ U’ U’ U U’ S5 S4 S3 U’ U’ U U C=0 V=101 C=0 V=100 C=0 V=011 ( b ) Moore

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