ATM-Board Specification (Daughter board I/F)

1. ATM-Board Specification(Daughter　board　I/F) 2006.9.26 IWATSU TEST INSTRUMENTS CORP. Koji Ishikawa

2. Daughter board dimension • Outline size • 85mm(H) × 120mm(W) • Thickness • 1.6mm max • It is recommended to be less than 1.6mm for durability of stacking.

3. Daughter board dimension

4. Screw mounting • Mounting hole for metal spacer • There are 4 mounting hole to avoid coming out ATM board. • M3 screw and spacer are used to attach the ATM and DB. • All of mounting hole on both ATM and DB should have φ3.5mm in diameter. • It might be better that the mounting holes are isolated from beside ground plane. (see figure plz.) • We can provide these screw and spacer attaching with ATM board. Therefore Daughter board can be mounted on ATM by them.

5. Connector and Spacer for mounting • Connector location • There are two connectors on both ATM and DB. • P1 and P2 connector are located on the ATM board. • J1 and J2 connector are located on the Daughter board. • J2 and J3 proposed by BU had unified into one J2 connector, and J2 and J1 connectors are located with the same way to ensure matching P1/2 on ATM and J1/2 on DB. • Stacking connectors • The daughter board is mounted by facing downward to the ATM board. • J1 connector is stacked for P1 on ATM, and J2 is stacked for P2. • FX6-80S-0.8SV connectors of HIROSE are used for P1 and P2 on ATM. • FX6-80P-0.8SV2 connectors of HIROSE are used for J1 and J2 on DB. • The stack height between parts face of DB and that of ATM should be less than 7mm. • All of parts on the daughter board must be avoid to contact with surface of the ATM board. • Except for P1,P2 and four spacers ,there will be no parts on the mounting area (120mm x 85mm) of ATM board.

6. Stacking formation • Stacking formation view

7. P1,P2 connectors pinout • P1,P2 on the ATM borad are located as the following figure.

8. Signal lines wiring

9. Power specification • V1 power source • Supply voltage :　+15V • V1power is directly provided from TKO backplane. • Absolute maximum current is totally 15A in two crate. So it is required that one daughter-board has low electricity consumption less than 0.5A.

10. Clock specification • Frequency: 60MHz →　The FPGA(SIC) on ATM board supplies this clock by redirecting from Local clock on ATM board. • Stability: less than 100ppm • Jitter 100ps peak to peak (T.B.D) → Outcome is merely wired without PLL processing in FPGA. → If this would be processed with PLL, the value of jitter will be estimated less than 0.02UI. • Signal standard: differential LVDS 2.5V

11. Clock distribution • Clock distribution on the ATM board

12. Clock domain allocation • Local clock should be available to operation whenever external system clock had come off illegally.

13. Pinout information • ATM board • RJ-45 connector • Ethernet control signals are connected • Pinouts are conformed to the MDI interface standard. • P1 connector • Enhanced interface signals are routed to this connector. • P2 connector • Ethernet signals and LED control signals are routed to this connector. • V1 power line is routed to this connector(#45-51, #59-65). • Daughter board • J1 connector • Enhanced interface signals are routed to this connector. • J2 connector • Ethernet signals and LED control signals are routed to this connector. • V1 power line is routed to this connector (#45-51, #59-65).

14. Pinout information • P1 connector pinout information

15. Pinout information • P2 connector pinout information

16. Pinout information • RJ-45 connector pinout information

17. Ground allocation • Stacking connector • Ground pattern area must be fortified with outside allocated area of connectors,J1and J2. • Ethernet signal lines that routed form P2 to RJ-45 are isolated from the signal ground by using such as gapped area. This way also will be need for the daughter board. • Metal spacer • There are some small through via hole around the Φ3.5mm hole for screw mounting. • This way is effective for stable contact to the signal ground.

18. TKO interface • Enhanced　TKO interface • Data handshaking of TKO interface is communicated through P1and J 1connectors. • All of signals use 2.5V LVCMOS logic levels. • Almost of the all FPGA devices have the slow slewrate function. This function will improve the quality of signal transmission. • There will be series damping resistors for the same reason above.

19. TKO interface • Enhanced-TKO Interface　READ cycle timing chart Slave Master ATM  Daughter board (computer) ‘IN’ are driven by the daughter card

20. TKO interface • Enhanced-TKO Interface　WRITE cycle timing chart Master Slave Daughter board (computer)  ATM ‘IN’ are driven by the daughter card

21. Ethernet Interface • Ethernet interface • Serial data is communicated by sending or receiving between P2 and J 2 connector. • Serial data line(Tx+, Tx-, Rx+, Rx-) should be well isolated from the signal GND. • Two LEDs are used to indicate for Network　status. • There is no label on the LEDs. • LED1 lights in green. LED2 lights in yellow.　 • On the ATM board, serial data lines are merely wired to RJ-45 connector placed at front side panel.

22. JTAG interface specification • JTAG interface specification • 4-wire interface • TCK JTAG　test clock • TDI JTAG　test data input • TMS JTAG　test mode select • TDO JTAG test data output • Vccj needs to be provided 3.3V level to conform with other JTAG devices. • TCK　clock frequency must be less than 25MHz. • JTAG interface is operated by IEEE1149.1. • JTAG interface can be used to configureFPGA and SPI flash memory that redirected by master FPGA.

23. Global Trigger specification • Global trigger interface specification • G_TRG signal is used for detection of global trigger. • Logic level LVCMOS 2.5V • Function If global-trigger is detected by SIC, G-TRG line goes to active high level for two clock cycles (33.3ns ). Daughter-board can use this line to manage the timing for access data by counting G_TRG pulses.

24. TKO address map • Summary of TKO address map • The daughter board can read-out the hit-data accessing Function0 address. • About details of the registers, it is not prepared to define

25. Summary architecture of DATA Format • Basic format： • 6byte Encapsulation -> form as 1 Cell • One cell consists of 6 bytes for each format. • Header - ID • length：　4bit • The value of 4bit-ID identifies classification of the defined 4-cells. • Hit-DATA • Spacer • RAW-DATA • Status-massage

26. DATA Format • ReadOut cell’s common format

27. DATA Format • Hit-DATA cell • Function • This cell contains the Hit-data which is captured in ATM board. • Header-ID value • Upper 4bitof channel number field is used to identify the cell. • value = 0000(b)　～　1011(b)　（applying for Signal-Ch0 ～　Ch23） • 6 bytes encapsulation • Length: 6 bytes • Raw data from TDC is formed into 6 bytes. • Channel number • Length:　5bit （Upper 4bits is used for Header-ID commonly) • Event-number • length：　12bit • Local event number reading-out from TDC

28. DATA Format • Hit-DATA cell • TDC count value • length：　16bit, 0.52ns/LSB • Read-out count value from TDC • This value is allowed to count up to 65535, and it corresponds to 34.078us. • If there are multiple hits between one event , another Hit-data cell also include this count value. • Range • length：　2bit • Detect range is Small ,Medium or Large. Each range is encoded to 2bit value. • In the Narrow or Wide trigger case, optimum range detected by DSM is encoded into cell. • In the Pedestal or Calibration case, all of the 3-ranges is encoded into cell. • QTC gate count value • length：　11bit, 0.52ns/LSB • This value is allowed to count up to 2027, and it corresponds to 1064ns. • Difference count between T2 and T1. T1 is rising edge time count. T2 is falling edge count. • Trigger ID • length：　2bit • Used to detect Narrow/Wide/Pedestal/Calibration

29. DATA Format • Hit-DATA cell • Format change • QTC gate count needs to be changed to extend the count range. • 10bits length of QTC gate_count -> 11bits length • 17bits length of TDC count -> 16bit • Almost of all the items have arranged for separating by boundary. New format Current format

30. DATA Format • New Hit-DATA cell format

31. DATA Format • Spacer cell • Function • This cell is inserted every 64Global event number. It contains global event number and check data. • Header-ID value • length：　4bit • value = 1100(b) • 6 bytes encapsulation • Length: 6 bytes • Global event number • length：　28bit • This number is distributed from Mclock-module. • Original global event number is 32bits-length. DSM reject lower 4bits from original 32bits number. So 28bits number is stored in the cell. • Check data(16bit Sum) • length：　16bit • This value is added by every 16bit between all of the 64 event period. • The target cells for the Sum-calculation are Hit-DATA cells.

32. DATA Format • Spacer cell format

33. DATA Format • RAW-DATA cell • Function • This cell includes incoming 32bits raw-data from TDC’s FIFO. • Header-ID value • length：　4bit • value = 1101(b) • TDC-ID • length：　4bit • TDC-ID code is allocated to the TDC device on the ATM board. • RAW－DATA • length：　32bit • 32bits raw-data read out from TDC is stored into one RAW-DATA cell.

34. DATA Format • RAW-DATA cell format

35. DATA Format • RAW-DATA cell format :TDC-ID field

36. DATA Format • Status-message cell • Function • This cell informs status of events on the ATM board. • This will allow to get the error information without polling accesses from the host controller. • Header-ID value • length：　4bit • value = 1110(b) • Classification • length：　2bit • This code classifies device or circuit block on the ATM board. • Device-Number • length：　4bit • This code identifies the number of selected device on the ATM board. • Status-ADR • length：　6bit • Status value • Length: 32bit

37. DATA Format • Status-message cell format