Detectors and Analog Electronics

1. Detectors and Analog Electronics Bill Crain The Aerospace Corporation 310-336-8530 Bill.Crain@aero.org

2. Introduction • Design Overview • Requirements Flowdown • Detector Specification • Signals, Noise, and Processing • Board Descriptions • Interface Diagram • Power Consumption • Trade Studies • Summary

3. Detector Electronics Design Overview • Electronic Board Designs • Telescope Board • Analog Processing Board (APB) in E-box • Heritage approach from Polar CEPPAD/IPS unchanged from proposal • Linear pulse processing system with Amptek front-end • Circuits designed specifically for CRaTER requirements • Functional requirements summary • Measure LET of high LET particles in thin detectors • Measure LET of low LET particles in thick detectors • Provide good resolution for TEP effects • Robust to temperature drift and environments

4. Detector Boards Telescope Board Analog Processing Board Thin Shaping Preamps Thick Scaling To Digital Board Thin Bias Networks Thick Baseline Restorer Thermistor Thin Timing Trigger Thick Functional Block Diagram

5. Analog Signal Flow Diagram • Single fixed gain, linear transfer function • All detector channels use same topology

6. Requirements Traceability

7. Detector Specification (1) • Document 32-05001 released rev 02 August 1, 2005 • Micron Semiconductor Limited • Lancing Sussex, UK • 20 years experience in supplying detectors for space physics • CEPPAD, CRRES, WIND, CLUSTER, ACE, IMAGE, STEREO, and more… • Detector Type • Ion-implanted doping to form P+ junction on N-type silicon • Very stable technology • Advantages to science include good carrier lifetime, stable to environmental conditions, and thin entrance windows

8. Active Dimension (35mm) ~ 1mm Gd/FP P+ Contact Grid Gd/FP P+ implant window 0.1 um Active Volume (depletion region) Thickness 140 um thin; 1,000 um thick E-field N window 0.1 um N contact Detector Specification (2) • Circular detectors having active area of 9.6 cm2 • Two different detector thicknesses: thin and thick • note: state-of-the-art is 20um for thin and 2,000um for thick detectors • Guard ring on P-side to improve surface uniformity • Very thin dead layers (windows) reduce energy loss, lower series resistance, and reduce noise

9. Guard ring Al. contact plane Al. contact grid reduces surface resistivity Detector Specification (3) • Detector drawings (Micron) • Note: this is not the present mount design

10. Requirement Specification Active area 9.6 cm2 circular Active dimension 35 mm Active dimension tolerance +/- 0.1 mm Thickness Thin = 140 um, Thick = 1000 um Thickness tolerance +/- 10 um Thickness uniformity +/- 10 um Window 0.1 um ohmic, 0.1 um junction Metalization Ohmic surface and junction grid 3000 Å +/- 1000 Å Full depletion (FD) Thin = 20 – 40V, Thick = 150 – 200V Operating voltage max Thin = 2 x FD, Thick = FD + 30V Capacitance Thin = 700 pF, Thick = 100 pF Leakage current max (20C) Thin = 300 nA junction, 200 nA guard Thick = 1,000 nA junction, 700 nA guard Drift (max leakage @ 40C) 6 x Ileak @ 20C Stability 1% Ileak @ 40C for 168 hours Alpha resolution Thin = 45 KeV, Thick = 35 KeV FWHM Detector Design Requirements Summary

11. Detector Specification (4) • ISO9001 • Full traceability and serialization • Travelers maintained • Qualification tests prior to flight detector shipment • Bond pull test • Random vibration test • Thermal cycling • Stability • Verification matrix specifies test criteria • Leakage current • Capacitance • I-V characteristic • Alpha resolution / pulser noise measurement

12. Detector Verification Matrix Eye Chart From 32-05001 Rev 02

13. Nominal Threshold Nominal Threshold Proton Energy Deposition Simulations Reference: M. Looper GEANT4 Thin 150MeV incident E Thick 150MeV incident E Thin 1000MeV incident E Thick 1000MeV incident E

14. Iron Energy Deposition Simulation Reference: J.B. Blake

15. RFB CFB Ao Vpk = Qtot/CFB qμnNe(t)E qμpNh(t)E Cdet CFB (Ao) >> Cdet Signal Characteristics

16. Signal Processing (1) • Combined dynamic range of thin/thick pair is 5,000 • Thin threshold to provide overlap with thick range • Thin Detector Signal • Preamp input stage designed for 97% charge collection • High gain input jFET for large dynamic input capacitance • 4% drift in operating point will result in 0.1% in output peak • Large feedback capacitance needed to handle Fe deposit • Preamp compensation to maintain closed-loop stability • Thick Detector Signal • Not as sensitive to detector capacitance • Designed for low noise to maintain reliable 200 KeV low threshold and meet resolution requirement

17. + input cap. T=peaking time F=shaping factors Noise Model (1) Reference: Helmuth Spieler IFCA Instrumentation Course Notes 2001

18. Noise Model (2)

19. Noise Model (3) 20C BOL

20. Signal Processing (2) • Noise dominated by thick detector leakage current • Shaping time same for both thin and thick detectors • ~1 usec for comfortable PHA input timing • 3-pole gaussian shaping improves symmetry • 2-complex poles shortens tail • Coincidence Timing • Noise occupancy in 1-usec coincidence window < 0.1% • Threshold to noise ratio (T/N) ~ 3.2 for timing discriminator • Timing discriminator threshold ~ 130 keV • Anticipated BOL T/N ratio is ~ 10 • Allows margin for leakage current drift up to 10 uA

21. Signal Processing (3) • Other factors affecting noise performance • Bias resistor on thin detector sized to minimize voltage drop • Bias resistor on thick detector sized to minimize noise • Detector shot noise doubles every 8 C • Beneficial to operate cold; preferably below 20 C

22. Signal Processing (4) • Pileup is rare due to low event rate and relatively short shaping time • Exception: occasional periods of high ESP flux • Coincidence timing uncertainty from leading edge trigger is small • Amplified timing discriminator reduces time walk to acceptable 10% uncertainty • Ballistic deficit is not an issue due to short collection times relative to peaking time of shaper • Output voltage scaled for PHA input specifications

23. Telescope Board Details • Thin/thick detector pair use same design topology • Signal collected on P-contact • Guard signal shunted to ground • No guard leakage noise • AC coupling to isolate DC detector leakage current • Low noise / high gain JFET input stage (InterFET) with Amptek A250 hybrid • MIL-STD-5510 polyimide 8-layer construction

24. Analog Processing Board Details • Single board in E-box contains 3 thin and 3 thick detector processing channels • Polyimide laminate, MIL-STD-55110, 8-layers, 0.062 in. • Interfaces to digital board in same box • Components • Linear Technology radiation tolerant opamps for shaping stages, BLR, and comparators • Analog Devices rad tolerant op-amp for test pulser interface and bias monitoring (see trade study chart) • Pole-zero cancellation circuit included to prevent undershoot

25. Analog Interface Block Diagram • ICD 32-02052 rev 01 • +/- 6V power, 5V • Thin and thick bias voltages • Unipolar gaussian signals input to peak-hold circuits • Low-level triggers for coincidence timing • Test pulser level and clocking signals

26. Power Estimate Total estimated power dissipation is < 1 Watt

27. Trade Studies • Considering detector bias current monitor • Housekeeping item to provide leakage current for each detector • No impact on noise or failure modes • Useful for diagnostic purposes especially during environmental testing of flight units

28. Summary • Detectors are well-established technology from experienced supplier • Detector specification and Analog/Digital ICD documents have been released • Electronics design meets requirements of instrument requirements document 32-01205