EE2174: Digital Logic and Lab

1. EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 9 Sequential Circuits

2. Sequential Circuits • Combinational Logic: • Output depends only on current input • Able to perform useful operations (add/subtract/multiply/…) • Require cascading of many structures • Costly and inflexible Chapter 9: Sequential Circuits

3. Sequential Circuits (cont.) • Sequential Logic: • Output depends not only on current input but also on past input values • Store information between operations (no need for cascading) • Need some type of memory to remember the past input values Chapter 9: Sequential Circuits

4. Sequential Circuits (cont.) Information Storing Circuits Circuits that we have learned so far Timed “States” Chapter 9: Sequential Circuits

5. Sequential Logic: Concept • Sequential Logic circuits remember past inputs and past circuit state. • Outputs from the system are“fed back” as new inputs (usually with delay). • The storage elements are circuits that are capable of storing binary information: memory. Chapter 9: Sequential Circuits

6. Synchronous vs. Asynchronous machines There are two types of sequential circuits: • Synchronous (latch mode) sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. • Asynchronous (fundamental mode) sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless). Chapter 9: Sequential Circuits

7. Clock Signal Clock generator: Periodic train of clock pulses Different duty cycles Chapter 9: Sequential Circuits

8. Synchronous Sequential Circuits:Flip flops as state memory • The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulses at fixed intervals of time, as shown in the timing diagram. Chapter 9: Sequential Circuits

9. Storing Elements Can’t change the stored value! Inverters Buffers Chapter 9: Sequential Circuits

10. S’R’ Latch (NAND version) S’ R’ Q Q’ 0 S’ 1 Q 0 0 0 1 1 0 1 1 1 0 Set 0 Q’ 1 R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 Chapter 9: Sequential Circuits

11. S’R’ Latch (NAND version) S’ R’ Q Q’ 1 S’ 1 Q 0 0 0 1 1 0 1 1 1 0 Set 0 Q’ 1 1 0 Hold R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 Chapter 9: Sequential Circuits

12. S’R’ Latch (NAND version) S’ R’ Q Q’ 1 S’ 0 Q 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 0 1 0 Hold R’ X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 Chapter 9: Sequential Circuits

13. S’R’ Latch (NAND version) S’ R’ Q Q’ 1 S’ 0 Q 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 1 1 0 Hold R’ 0 1 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 Chapter 9: Sequential Circuits

14. S’R’ Latch (NAND version) S’ R’ Q Q’ 0 S’ 1 Q 1 1 Disallowed 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 Q’ 0 1 0 Hold R’ 0 1 Hold X Y NAND 0 0 1 0 1 1 1 0 1 1 1 0 Chapter 9: Sequential Circuits

15. SR Latch with Clock signal Latch is sensitive to input changes ONLY when C=1 Chapter 9: Sequential Circuits

16. S CLK R S R CLK S’ R’ Q Q’ SR Latch with Clock signal (cont.) S’ Q Q’ R’ 0 0 1 1 1 Q0 Q0’ Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q0 Q0’ Store Chapter 9: Sequential Circuits

17. D Latch • One way to eliminate the undesirable indeterminate state in the RS latch is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch: Chapter 9: Sequential Circuits

18. D D CLK Q Q’ 0 1 0 1 1 1 1 0 X 0 Q0 Q0’ D Latch (cont.) S S’ Q CLK Q’ R R’ S R CLK Q Q’ 0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Store Chapter 9: Sequential Circuits

19. D Latch with Transmission Gates 1 2 • C=1  TG1 closes and TG2 opens  Q’=D’ and Q=D • C=0  TG1 opens and TG2 closes  Hold Q and Q’ Chapter 9: Sequential Circuits

20. Flip-Flops • Latches are “transparent” (= any change on the inputs is seen at the outputs immediately). • This causes synchronization problems! • Solution: use latches to create flip-flops that can respond (update) ONLY on SPECIFIC times (instead of ANY time). Chapter 9: Sequential Circuits

21. Alternatives in FF choice • Type of FF • RS • D • JK • Type of triggering • Untriggered (asynchronous) • Level-triggered (C=1) • Edge-triggered (rising or falling edge of C) Chapter 9: Sequential Circuits

22. Master-Slave FF configuration using SR latches Chapter 9: Sequential Circuits

23. Master-Slave FF configuration using SR latches (cont.) S R CLK Q Q’ • When C=1, master is enabled and stores new data, slave stores old data. • When C=0, master’s state passes to enabled slave (Q=Y), master not sensitive to new data (disabled). 0 0 1 Q0 Q0’ Hold 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 Q0’ Hold Chapter 9: Sequential Circuits

24. Master-Slave J-K Flip-Flop Chapter 9: Sequential Circuits

25. Flip-Flop Problem • The change in the flip-flop output is determined by the circuit frequency • S and/or R are permitted to change while C = 1 • Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 • The master latch sets to 1 • A 1 is transferred to the slave • Suppose that Q = 0 and S=1, R=0 -> S=0, R=0 -> S=0, R=1 -> S=0, R=0 • The master latch sets and then resets • A 0 is transferred to the slave Chapter 9: Sequential Circuits

26. Flip-Flop Solution • Use edge-triggering instead of master-slave • An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal • Edge-triggered flip-flops can be built directly at the electronic circuit level, or • A master-slave D flip-flop which also exhibits edge-triggered behavior can be used. Chapter 9: Sequential Circuits

27. Edge-triggered Flip-Flops • Attach level-triggered D to level-triggered SR, using complemented clocks. • D-Type Positive Edge-Triggered Flip-Flop: Chapter 9: Sequential Circuits

28. Characteristic Tables • Defines the logical properties of a flip-flop (such as a truth table does for a logic gate). • Q(t) – present state at time t • Q(t+1) – next state at time t+1 Chapter 9: Sequential Circuits

29. Characteristic Tables (cont.) Chapter 9: Sequential Circuits

30. Characteristic Tables (cont.) Chapter 9: Sequential Circuits

31. Characteristic Tables (cont.) Characteristic Equation: Q(t+1) = D(t) Chapter 9: Sequential Circuits

32. Characteristic Tables (cont.) Obtained by JK Flip-Flop with J=K=T Characteristic Equation: Q(t+1) = T’Q(t) + TQ(t)’ Chapter 9: Sequential Circuits