ECE 332 Digital Electronics and Logic Design Lab

1. ECE 332 Digital Electronics and Logic Design Lab • Lab 3 • Introduction to Starter Kit ECE 332 George Mason University

2. Roadmap • Tool Start-up • Implementing an example on Kit • Introduction to VHDL ECE 332 George Mason University

3. Tools • Software tools used in this course are • Xilinx ISE 12.3 • Writing VHDL codes • Functional simulation (XST) • Synthesis and Implementation • Digilent CoolRunner-II • Power measurements ECE 332 George Mason University

4. Running a DEMO from CD • Open Digilent CoolRunner-II Utility • Program using the “jed” of handbook_example • Observe the power measurments ECE 332 George Mason University

5. Synthesis & Implementation • Download the sample VHDL and UCF files • Open Xilinx ISE 12.3 project manager • Implement the design and generate the “jed” file • Run the “jed” file using Diligent CoolRunner-II ECE 332 George Mason University

6. Introduction to VHDL • VHDL is not case sensitive • VHDL is a “free format” language. The spacing and carriage return are considered same. • Comments in VHDL are indicated by “double dash” i.e. “--” • File extension of a VHDL file is .vhd ECE 332 George Mason University

7. Introduction to VHDL cont... • VHDL is mainly divided into 3 sections LIBRARY ieee; USEieee.std_logic_1164.all; ENTITYnand_gateIS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); ENDnand_gate; ARCHITECTUREmodelOFnand_gateIS BEGIN z <= aNANDb; ENDmodel; LIBRARY DECLARATION ENTITY ARCHITECTURE ECE 332 George Mason University

8. Library Declarations LIBRARY ieee; USEieee.std_logic_1164.all; ENTITYnand_gateIS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); ENDnand_gate; ARCHITECTUREmodelOFnand_gateIS BEGIN z <= aNANDb; ENDmodel; Library declaration Use all definitions from the package std_logic_1164 ECE 332 George Mason University

9. LIBRARY library_name; USE library_name.package_name.package_parts; Library Declarations - Syntax ECE 332 George Mason University

10. ENTITYnand_gateIS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); ENDnand_gate; Entity Declarations • Entity is used to define the inputs and outputs of the system Entity name Port type Port names Semicolon No Semicolon after last port Reserved words Port modes (data flow directions) ECE 332 George Mason University

11. Entity Declarations - Syntax ENTITY entity_name IS PORT ( port_name : port_mode signal_type; port_name : port_mode signal_type; …………. port_name : port_mode signal_type); END entity_name; ECE 332 George Mason University

12. Architecture Declarations • Architecture describes functionality of the system • Architecture is used to define the interconnections and relations between inputs and outputs of the system ARCHITECTUREmodelOFnand_gateIS BEGIN z <= aNANDb; ENDmodel; ECE 332 George Mason University

13. Architecture Declarations - Syntax ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name; ECE 332 George Mason University