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CHAPTER 6 Virtex Memory

CHAPTER 6 Virtex Memory. Agenda. RAM Applications LUT RAM SRL 16 Other uses of LUT RAM (FIFO focus) Block RAM Inside Block RAM Cells. Operand stacks Register files Instruction caches DMA buffers Instruction memories State tables Logic functions Message buffers Virtual channels.

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CHAPTER 6 Virtex Memory

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  1. CHAPTER 6 Virtex Memory

  2. Agenda • RAM Applications • LUT RAM • SRL 16 • Other uses of LUT RAM (FIFO focus) • Block RAM • Inside Block RAM Cells

  3. Operand stacks Register files Instruction caches DMA buffers Instruction memories State tables Logic functions Message buffers Virtual channels Video line buffers Digital delay lines RAMDAC color mapping tables Test vector buffers PCI configuration space Sequential machines More . . . RAM Applications

  4. LUT/RAM/Shifter Structure

  5. Linear Feedback Shift Regs. Galois style Fibonacci style

  6. Multiple SRL16E LFSR

  7. Virtex 5 SRL 32s Cascaded

  8. Push/Pop Shifter

  9. Single and Dual Port LUT RAM

  10. Dual Port Distributed SRAM Detail

  11. Cascading LUTs for Depth

  12. Virtex 5 32 X 2 Dual Port LUT RAM

  13. Virtex 5 32 X 6 Dual Port LUT RAM

  14. Dual Port Select RAM FIFO

  15. Counter Structure

  16. Asynchronous FIFO Issues • Problems with separate clock domains • Speed discrepancy between the two domains • Possibility of overflowing • Arrival rate/departure rate problem • Status communication • Glitching conditions on counters • Metastability • Would like nice, tidy “always works” solutions • Full details in Sunburst Design writeup by Cummings & Alfke

  17. Asynchronous FIFO Control

  18. Virtex Family BRAMS

  19. 256 X 16 BRAM Module

  20. 256 X 32 BRAM Module

  21. 512 X 16 BRAM Module Comment: slide needs Inverter on one of the EN’s

  22. BRAM Specialized Interconnect

  23. BRAM Output Multiplexing

  24. BRAM/Multiplier Relationship

  25. Virtex II BRAM Approach

  26. 16 Bit SRAM Structure

  27. Single Storage Cell of SRAM

  28. Single Bit SRAM Read/Write Circuits

  29. 16 Bit Dual Port BRAM Structure

  30. 512 X 36 Bit FIFO

  31. Virtex 4 BRAM Symbol

  32. V4 BRAM Output Register Structure

  33. V4 BRAM Cascading Structure

  34. Virtex 4 FIFO Support Structure (this stuff is inside the V4 BRAM module, built in)

  35. 8K X 4 Virtex 4 FIFO Cascading like this requires a 2 IN NOR be built in the LUT fabric

  36. 512 X 72 Virtex 4 FIFO Cascading like this needs 2 AND, 2 OR and 2 Inverters in LUT fabric

  37. Virtex 5 Dual Port BRAM Symbol

  38. Virtex 5 BRAM Organized X 64

  39. Virtex 5 BRAM Configurable Options

  40. Virtex 5 BRAM Cascade

  41. V5 BRAM Output MUX/Cascade Circuitry

  42. Timing with/without Fall Through

  43. V5 BRAM 64 Bit ECC

  44. Virtex RAM Closing Comments • RAM may be the primary on board feature beyond fabric of general use • Makes having other on board resources more effective • FIFOs –fast cross clock domain interfacing • Microprocessors – code/data storage • DSPs – on chip operand storage • And so on . . . • See XAPP 463 (appendix) for Verilog/VHDL code listing for using BRAM structure.

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