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Wireless Terminal and PC Interface Using VLSI

Wireless Terminal and PC Interface Using VLSI. EE451 - Senior Project Members: Chris Brophy Matt Olinger Advisor: Dr. V. Prasad. 12/11/01. Outline. Summary Standards Functional Description Block Diagram Hardware Flow Chart Testing Preliminary Work

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Wireless Terminal and PC Interface Using VLSI

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  1. Wireless Terminal and PC Interface Using VLSI EE451 - Senior Project Members: Chris Brophy Matt Olinger Advisor: Dr. V. Prasad 12/11/01

  2. Outline • Summary • Standards • Functional Description • Block Diagram • Hardware Flow Chart • Testing • Preliminary Work • Schedule

  3. Summary • Provide an alternative for wireless terminals • Two interfaces are required: • ISA bus (from computer) • Proprietary bus interface (RF device) • A method of buffering is also necessary, since the data rates of both interfaces are unequal. • A status register is also necessary to provide feedback to the computer when to send, receive, etc…

  4. Standards • Industry Standard Architecture will be implemented • Provides compatibility to all “IBM clones” • Relatively simplistic design

  5. Functional Description • ISA interface • Data D0-D7 • Address A0-A9 • WR, RD, INT, BALE • RF module (depends on type) • Data D0-D3 + RXR, RXA, etc… • Serial Data • Software • Provides flow control, error correction, etc…

  6. Block Diagram • Control lines include: WR, RD, INT, BALE • Data D0-D7 to and from ISA and Buffer • Address lines to decoder

  7. Hardware Flow Chart

  8. Testing • Preliminary design in Logic Works and Renoir • Actual testing and simulation done on FPGA target • Cannot test fabricated chips until they come back • Unfortunately, they will not return until summer

  9. Preliminary Work • EE565 ISA bus design • Topics covered: • Timing Analysis / Design • Loading Analysis / Design • Address Decoding • Interrupt Control • x86 assembly language

  10. Preliminary Work • RF module research • Characteristic Considerations: • Cost • Range • Ease of interface • Availability – Is it legal in USA? • Support from company / distributor • VLSI gates and design project • Provides “building blocks” for actual design • “Paste” blocks where needed after circuit is designed

  11. Schedule • Dec – Jan (Break) • More “preliminary” design work (Begin Logic Gates) • Feb • Finish Logic Design • Begin Simulation • March • Finish Simulation / Begin drawing in LEDIT • Implement design on FPGA • April • Finish drawing gates in LEDIT

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