VLSI Design Using PC-Based Tools

1. VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady, NY PC-Based VLSI Design Tools Cherrice Traver

2. Why use PC-based tools? PC-Based VLSI Design Tools Cherrice Traver

3. Outline Tanner Research Tools for Education • Practical issues • Tool flow and capabilities • Example use • Curriculum examples PC-Based VLSI Design Tools Cherrice Traver

4. Practical IssuesSystem Requirements Minimumrequirements • 100 MHz PCs, 32M RAM Recommended • 500 MHz PCs, 256M RAM • 3-button mouse PC-Based VLSI Design Tools Cherrice Traver

5. Practical IssuesInstallation • Tool installation - Install-Shield Wizard • License server • Sentinel LM on NT Server • Floating individual tool licenses PC-Based VLSI Design Tools Cherrice Traver

6. Practical IssuesTool Choices L-Edit DRC EXT SPR L-Edit Pro CMOS Libraries Tspice S-Edit W-Edit T-Spice Pro Design Pro Tanner Tools Pro PC-Based VLSI Design Tools Cherrice Traver

7. Practical IssuesCost and Maintenance • Educational pricing • Quantity pricing • Free support for 60 days • No annual maintenance fee required • 15% maintenance fee per year for updates and continued support PC-Based VLSI Design Tools Cherrice Traver

8. Practical IssuesDocumentation Help Menu Indexed PDF Manual PC-Based VLSI Design Tools Cherrice Traver

9. Contact Information Janice Barthelemy Account Manager janice@tanner.com Tanner EDA 2650 East Foothill Blvd. Pasadena, CA 91107 Toll free (877) 325-2223 Fax (626) 792-0300 www.tanner.com PC-Based VLSI Design Tools Cherrice Traver

10. Simplified Tanner Tool Flow S-Edit TM Schematic Editor T-Spice TM Circuit Simulator W-Edit TM Waveform Viewer L-Edit TM Full Custom Layout Editor GDS II & CIF PC-Based VLSI Design Tools Cherrice Traver

11. Overview of Examples • Layout Editor - L-Edit • Schematic Editor - S-Edit • Standard Cell Place and Route - SPR • Spice simulator - T-Spice PC-Based VLSI Design Tools Cherrice Traver

12. L-Edit: Tool Flow S-Edit TM T-Spice TM Layout Libraries SCMOSLib ... L-Edit/SPR TM Standard Cell Place & Route L-Edit/Extract TM General Device Extractor L-Edit TM Full Custom Layout Editor L-Edit/DRC TM On-line Design Rule Checker Cross Section Viewer PC-Based VLSI Design Tools Cherrice Traver

13. L-Edit: Layout Editor Features PC-Based VLSI Design Tools Cherrice Traver

14. L-Edit: Example CMOS Inverter • Layout Editing • DRC • Cross Section Viewing • Extract Spice File PC-Based VLSI Design Tools Cherrice Traver

15. S-Edit: Tool Flow Technology Mapping Library SCMOS ... SchemLib TM Technology Independent Library S-Edit TM Schematic Editor netlist extract NetTran T-Spice TM SPR L-Edit TM PC-Based VLSI Design Tools Cherrice Traver

16. S-Edit: Schematic Editor Features PC-Based VLSI Design Tools Cherrice Traver

17. S-Edit: Example Full Adder Circuit • Schematic Drawing • Spice Export • Tanner Place and Route Export PC-Based VLSI Design Tools Cherrice Traver

18. SPR: Tool Flow S-Edit TM .tpr file Layout Libraries SCMOSLib ... L-Edit/SPR TM Standard Cell Place & Route L-Edit TM Full Custom Layout Editor PC-Based VLSI Design Tools Cherrice Traver

19. SPR: Example Full Adder Circuit • L-Edit - Place and Route • Core + Padframe • Extract Spice Circuit PC-Based VLSI Design Tools Cherrice Traver

20. T-Spice and W-edit: Tool Flow S-Edit TM netlist extract T-Spice TM Circuit Simulator W-Edit TM Waveform Viewer device extract L-Edit TM PC-Based VLSI Design Tools Cherrice Traver

21. T-Spice and W-edit: Features • Menu-based command insertion • Integrated W-Edit waveform viewer • Circuit Probing from S-Edit PC-Based VLSI Design Tools Cherrice Traver

22. T-Spice and W-edit: Example Full Adder simulation • Simulation of schematic netlist • Waveform probing • Simulation of extracted layout PC-Based VLSI Design Tools Cherrice Traver

23. Tool Integration in VLSI Design Course Laboratories • Tool use • Reinforcement of lecture topics Project • Behavior --> Layout design experience PC-Based VLSI Design Tools Cherrice Traver

24. Laboratories Lab 1 - L-Edit/T-Spice • Extract/simulate NAND gate • Layout/extract/simulate inverter Lab 2 - L-Edit/T-Spice • Manual placement/routing standard cells • Manual stick diagrams • Extraction/simulation Lab 3 - S-Edit/L-Edit/SPR/T-Spice • Schematic capture - netlist simulation • Standard cell place/route PC-Based VLSI Design Tools Cherrice Traver

25. Kitchen Timer Projectfrom Modern VLSI Design: Systems on Silicon, Wayne Wolf PC-Based VLSI Design Tools Cherrice Traver

26. Buzz Circuit Schematic Given - Lab Exercise PC-Based VLSI Design Tools Cherrice Traver

27. Display Circuit Block Diagram Given - Lab Exercise PC-Based VLSI Design Tools Cherrice Traver

28. Controller • Specified by state diagram and VHDL model • Logic simulation outputs provided PC-Based VLSI Design Tools Cherrice Traver

29. Timer PC-Based VLSI Design Tools Cherrice Traver

30. Support Provided • VHDL “Golden” behavioral model • Simulation output results • Lots of guidance on debugging PC-Based VLSI Design Tools Cherrice Traver

31. Top Level Schematic PC-Based VLSI Design Tools Cherrice Traver

32. Kitchen Timer Chip Statistics • 600 Gates • 8000 Transistors • Layout area: 1550 um x 1375 um PC-Based VLSI Design Tools Cherrice Traver

33. Final Layout PC-Based VLSI Design Tools Cherrice Traver

34. MOSIS Fabrication • Pads provided • Flatten layout • Export CIF file PC-Based VLSI Design Tools Cherrice Traver

35. Other Past DesignsUsing Tanner Tools • Quadrature Decoder http://doc.union.edu/154/Quad.decode.project/index.html • Simple Floating-Point Multiplier http://doc.union.edu/154/Mult.project/mult.project.html PC-Based VLSI Design Tools Cherrice Traver

36. Conclusion • Ease of Installation/Maintenance • Reasonable Design Flow • Good Interface for MOSIS Fabrication PC-Based VLSI Design Tools Cherrice Traver