1 / 24

Cross Hole Ultrasonic Monitor

High Speed Digital Signal Lab. Cross Hole Ultrasonic Monitor. Part A Presentation. Students : Lotem Sharon Yuval Sela. Instructor : Ina Rivkin. Background. Cross Hole Ultrasonic Monitor (CHUM) system made by Piletest Quality control of deep concrete foundation

quinn-heath
Download Presentation

Cross Hole Ultrasonic Monitor

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. High Speed Digital Signal Lab Cross Hole Ultrasonic Monitor Part A Presentation Students: Lotem Sharon Yuval Sela • Instructor : Ina Rivkin

  2. Background • Cross Hole Ultrasonic Monitor (CHUM) system made by Piletest • Quality control of deep concrete foundation • Ultrasonic waves through the concrete • Measuring the energy and the first arrival time

  3. Motivation • The current CHUM uses sample rate of 500kHz, complying American standard. • A necessity came up to comply with the 1MHz French standard.

  4. Goal • Developing a board based on FPGA, that samples data at rates of up to 1MHz, and connects to the Motherboard. • Enabling a high sampling rate and a slow data transfer rate to the MC by FPGA configured as a FIFO and as a data flow controller.

  5. Data Flow Scheme • Analog Devices AD7671 LQFP48 Analog to Digital Converter • Altera FPGA Cyclone IV EP4CE6 EQFP144 • Texas Instruments Micro-Controller MSP430F5419AIPZ, on the motherboard High speed Low speed To user interface Micro-Controller Analog from Rx FPGA (FIFO) ADC 1MHz

  6. System Overview Motherboard - Power Supply Circuit - Microcontroller - Test Circuit - Variable-Gain Amplifier - Emitter Circuit Daughter Board

  7. Project Overview Part I • Electrical scheme • PCB design • PCB manufacturing & assembly • Board power supply and FPGA examination Part II • Board examination • FPGA logic design: FIFO & state machine • Microcontroller software • Whole system operation examination • Flash configuration device

  8. Our Board JTAG Oscillator 16-Bit Data 8-Bit Data ADC FPGA POWER Clock Control Control Motherboard RESET Analog input PROM

  9. Top JTAG Connector ADC FPGA Connectors Motherboard connectors

  10. Connectors

  11. FPGA Power

  12. FPGA I/O

  13. FPGA Configuration (0,1,0) -> (1,0,0)

  14. ADC

  15. Oscillator

  16. PCB Design 6 layers:

  17. Structure of Our Board FPGA Flash Config. Device ADC Operational Amplifier & Voltage Reference Serial Resistors JTAG & Motherboard Connectors

  18. Successful Tests • Electrical verification: GND & supplies • FPGA recognition via JTAG • JTAG configuration • Simple design trial run, using CLK from the MC (motherboard) and SignalTap

  19. Part B Characterization

  20. System Integration Motherboard Daughterboard Receiver circuit Analog Analog Ultrasound receiver ADC 16 Control (FPGA) Emitter circuit Ultrasound emitter USB FIFO (FPGA) User Interface 8 Software (Microcontroller)

  21. FPGA Top Level Design <- ADC Motherboard -> Controller (VHDL State Machine)

  22. FPGA State Machine St. Mach. Start=0 Sample Rate=0 Busy=1 Idle Sample Rate=1 Busy=0 FIFO Full=0 wrclk = 1 Rdclk = 1 FIFO Full=1 Count=0 St. Mach. Start=1 FIFO RD=1 wrfull=0 STMACH_RST=1 Rdclk = 0 wrfull=1 FIFO RD=1 FIFO RD=0 H/L Byte =1 FIFO RD=1 FIFO RD=1 FIFO RD=0 H/L Byte =0 FIFO RD=0 Rdclk = 1 FIFO RD=0 FIFO RD=0

  23. Microcontroller Software • Interface to UI computer • Data transfer from FPGA to the computer • Receiver circuit gain control • Emitter control • Self test simulation control

  24. Gantt

More Related