Dynamic software reconfiguration using control supervisors

1. Dynamic software reconfigurationusing control supervisors Ugo Buy 13 June 2005

2. Background • Concurrent, distributed applications are commonplace • Often subject to real-time constraints • Possibility of concurrency errors (e.g., mutex violations, deadlocks) and real-time errors (e.g., missed deadlines) • Difficult errors to detect through traditional testing • Non-deterministic behavior • Non-repeatable errors • Solution: Model relevant aspects of software behavior; analyze with formal methods and simulation

3. Analysis strategies • Formal verification: Automatically check whether a system model satisfies desired concurrency and timing properties • Can exhaustively detect all potential defects • High computational complexity; difficult to scale • Widely explored, mature technologies • Applied to real-world design problems (both hardware and software) with increasing frequency • Typically work on finite state automata or Petri nets

4. Analysis strategies • Supervisory control of discrete event systems Given system model, add controller enforcing desired concurrency and timing properties to model • Often more tractable than verification • Support dynamic reconfiguration through automatic supervisor synthesis • Similar models to verification (e.g., finite state automata and Petri nets)

5. Current project • Dynamic reconfiguration of discrete manufacturing systems • Funding from NIST in collaboration with Starthis, Inc. • Rationale: • Control programs are hard to write and maintain • Flexible manufacturing demands rapid reconfiguration • Possibility of deadlock, mutex violations, deadline violations in manufacturing plants • Disastrous consequences sometimes possible

6. Approach • Avoid verification complexity with supervisory control • Petri nets vs. finite state automata • Synthesis of deadline-enforcing supervisors using net unfolding • Compositional methods (e.g., hierarchical control)

7. GUI Plant spec Constraints Control code SFCs TPNs Translator Supervisor generator Code generator Refined TPNs Flow of supervisory synthesis • Specify plant behavior and correctness properties • Generate Petri net • Synthesize control supervisor • Generate target code

8. Achievements to date • System for enforcing deadlines on transition firing in time Petri nets • Integration of methods for enforcing mutual exclusion and freedom from deadlock • Framework for compositional analysis (hierarchical control)

9. Additional research • Decision support for emergency response during mass casualty situations • Collaboration with Prof. Houshang Darabi and his group in Industrial Engineering • Model healthcare, transportation and communication systems needed for emergency response • Work local government agencies involved in emergency response

10. Potential collaborations • Strong software engineering group at UIC • Tadao Murata • Sol Shatz • Jeffrey Tsai • Prasad Sistla • Lenore Zuck • Additional strengths in computer security, transportation systems