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Understand Cache Memory Basics for Microprocessors

Learn about cache memory, its importance for microprocessors, different mapping techniques, write policies, cache coherence protocols, and common terminology in computer architecture. Includes a glossary and references.

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Understand Cache Memory Basics for Microprocessors

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  1. Snoop cache AMANO, Hideharu, Keio University hunga@am．ics．keio．ac．jp Textbookpp.40-60

  2. Cache memory • A small high speed memory for storing frequently accessed data/instructions. • Essential for recent microprocessors. • Basis knowledge for uni-processor’s cache is reviewed first.

  3. Yes：Hit Data 010 010 Direct Map From CPU 0011010 0011 010 100 … … Main Memory (1KB=128Lines) = 0011 Cache (64B=8Lines) Cache Directory (Tag Memory) 8 entries X (4bit ) Simple Directory structure

  4. No: Miss Hit 010 010 Direct Map (Conflict Miss) From CPU 0000010 0000 010 100 … … Main Memory = 0011 0000 Cache Conflict Miss occurs between two lines with the same index Cache Directory (Tag Memory)

  5. Yes: Hit Data 10 0 10 2-way set associative Map From CPU 0011010 00110 10 100 … … Main Memory (1KB=128Lines) = 00110 Cache (64B=8Lines) No = 00000 Cache Directory (Tag Memory) 4 entries X 5bit X 2

  6. Yes: Hit 10 1 10 Data 2-way set associative Map From CPU 0000010 0011010 00000 10 100 … … Main Memory (1KB=128Lines) No = 00110 Cache (64B=8Lines) = 00000 Cache Directory (Tag Memory) 4 entries X 5bit X 2 ConflictMiss is reduced

  7. 0011 010 100 Hit WriteThrough　（Hit） 0011010 … … From CPU Main Memory (1KB=128Lines) The main memory is updated 0011 Cache (64B=8Lines) Write Data Cache Directory (Tag Memory) 8 entries X (4bit )

  8. 0000 010 100 Miss WriteThrough　（Miss：DirectWrite） 0000010 0011010 … … From CPU Main Memory (1KB=128Lines) Only main memory is updated 0011 Cache (64B=8Lines) Write Data Cache Directory (Tag Memory) 8 entries X (4bit )

  9. 0000 010 100 Miss WriteThrough　（Miss：Fetch on Write） 0000010 0011010 … … From CPU Main Memory (1KB=128Lines) 0011 0000 Cache (64B=8Lines) Write Data Cache Directory (Tag Memory) 8 entries X (4bit )

  10. 0011 010 100 Hit Write Back　（Hit） 0011010 … … From CPU Main Memory (1KB=128Lines) Dirty 1 0011 Cache (64B=8Lines) Write Data Cache Directory (Tag Memory) 8 entries X (4bit+1bit )

  11. 0000 010 100 Write Back Miss WriteBack　（Replace） 0000010 0011010 … … From CPU Main Memory (1KB=128Lines) Dirty 1 0011 0000 0 Cache (64B=8Lines) Cache Directory (Tag Memory) 8 entries X (4bit+1bit )

  12. Shared memory connected to the bus • Cache is required • Shared cache • Often difficult to implement even in on-chip multiprocessors • Private cache • Consistency problem → Snoop cache

  13. PE PE PE PE Shared Cache Bus Interface MainMemory Shared Cache • 1 port shared cache • Severe access conflict • 4-port shared cache • A large multi-port memory is hard to implement Shared cache is often used for L2 cache of on-chip multiprocessors

  14. Snoop Cache Snoop Cache Snoop Cache PU PU PU Ｐｒｉｖａｔｅ（Snoop）　Cache MainMemory Alargebandwidthsharedbus Snoop Cache PU Each PU provides its own private cache

  15. Bus as a broadcast media • A single module can send (write) data to the media • All modules can receive (read) the same data →　Broadcasting Tree Crossbar + Bus Network on Chip (NoC) • Here, I show as a shape of classic bus but remember that it is just a logical image.

  16. PU PU PU Cache coherence (consistency) problem MainMemory Alargebandwidthsharedbus A A’ A PU Data of each cache is not the same

  17. Coherence vs. Consistency • Coherence and consistency are complementary： • Coherence defines the behavior of reads and writes to the same memory location, while • Consistency defines the behavior of reads and writes with respect to accesses to other memory location. Hennessy & Patterson “Computer Architecture the 5th edition” pp.353

  18. CacheCoherenceProtocol • Each cache keeps coherence by monitoring (snooping) bus transactions. WriteThrough：Every written data updates the shared memory. Frequent access of bus will degrade performance Basis（Synapse) Ilinois Berkeley Invalidate WriteBack: Update (Broadcast) Firefly Dragon

  19. Glossary 1 • Shared Cache:共有キャッシュ • Private Cache:占有キャッシュ • SnoopCache:スヌープキャッシュ、バスを監視することによって内容の一致を取るキャッシュ。今回のメインテーマ、ちなみにSnoopは「こそこそかぎまわる」という意味で、チャーリーブラウンに出てくる犬の名前と語源は(多分）同じ。 • Coherent（Consistency) Problem:マルチプロセッサで各PEがキャッシュを持つ場合にその内容の一致が取れなくなる問題。一致を取る機構を持つ場合、Coherent Cacheと呼ぶ。ConherenceとConsistencyの違いは同じアドレスに対するものか違うアドレスに対するものか。 • Direct map:ダイレクトマップ、キャッシュのマッピング方式の一つ • n-way set associative:セットアソシアティブ、同じくマッピング方式 • Write through, Write back:ライトスルー、ライトバック、書き込みポリシーの名前。Write throughは二つに分かれ、Direct Writeは直接主記憶を書き込む方法、Fetch on Writeは、一度取ってきてから書き換える方法 • Dirty/Clean:ここでは主記憶と内容が一致しない/すること。 • この辺のキャッシュの用語はうまく翻訳できないので、カタカナで呼ばれているため、よくわかると思う。

  20. Ｒｅａｄ Ｒｅａｄ PU PU PU Ｗｒｉｔｅ　Ｔｈｒｏｕｇｈ　Ｃａｃｈｅ（Invalidation：Data read out） Ｉ：Invalidated Ｖ：Valid MainMemory Alargebandwidthsharedbus Ｖ Ｖ PU

  21. Ｗｒｉｔｅ PU PU PU Ｗｒｉｔｅ　Ｔｈｒｏｕｇｈ　Ｃａｃｈｅ（Invalidate：Data write into） Ｉ：Invalidate Ｖ：Valid MainMemory Alargebandwidthsharedbus Monitoring (Snooping) Ｖ I Ｖ PU

  22. Monitoring (Snooping) Ｗｒｉｔｅ PU PU PU Ｗｒｉｔｅ　Ｔｈｒｏｕｇｈ　Ｃａｃｈｅ（InvalidateDirectWrite) The target cache line is not existing in the cache Ｉ：Invalidated Ｖ：Valid MainMemory Alargebandwidthsharedbus V I PU

  23. First, Fetch Monitoring (Snoop) Ｗｒｉｔｅ PU PU PU Ｗｒｉｔｅ　Ｔｈｒｏｕｇｈ　Ｃａｃｈｅ（Invalidate：FetchOnWrite） Cache line is not existing in the target cache Ｉ：Invalidated Ｖ：Valid MainMemory Alargebandwidthsharedbus Ｉ Ｖ Ｖ PU Fetch and write

  24. Ｗｒｉｔｅ PU PU PU Ｗｒｉｔｅ　Ｔｈｒｏｕｇｈ　Ｃａｃｈｅ（Update） Ｉ：Invalidated Ｖ：Valid MainMemory Alargebandwidthsharedbus Monitoring (Snoop) Ｖ V Data is updated PU

  25. The structure of Snoop cache Shared bus Directory can be accessed simultaneously from both sides. The bus transaction can be checked without caring the access from CPU. Directory CacheMemory Entity The same Directory (DualPort) Directory CPU

  26. Quiz Following accesses are done sequentially into the same cache line of Write throughDirect Write and Fetch-on Write protocol. How the state of each cache line is changed ? PU A: Read PU B: Read PU A: Write PU B: Read PU B: Write PU A: Write

  27. The Problem of WriteThroughCache • In uniprocessors, the performance of the write through cache with well designed write buffers is comparable to that of write back cache. • However, in bus connected multiprocessors, the write through cache has a problem of bus congestion.

  28. Read Read PU PU PU Basic Protocol States attached to each line C：Clean (Consistent to shared memory) D: Dirty I：Invalidate MainMemory Alargebandwidthsharedbus C C PU

  29. Invalidation signal Write PU PU PU Basic Protocol（A PU writes the data） MainMemory Alargebandwidthsharedbus C I D C PU Invalidation signal: address only transaction

  30. Read PU PU PU Basic Protocol (A PU reads out) MainMemory Alargebandwidthsharedbus C I C D PU

  31. Snoop Cache Snoop Cache W PU PU PU Basic Protocol (A PU writes into again) MainMemory Alargebandwidthsharedbus D I I D PU

  32. State Transition Diagram of the Basic Protocol write miss for the block write I I write miss read Replace Write back & Replace Replace write hit D Invalidate Invalidate write miss read miss for the block Replace D C C read miss Write back & Replace read miss Replace Bus snoop request CPU request

  33. CE CS Snoop Cache Snoop Cache CS PU PU PU States for each line Illinois’s Protocol CE：CleanExclusive CS：CleanSharable DE：DirtyExclusive I：Invalidate MainMemory Alargebandwidthsharedbus PU

  34. CE Snoop Cache Snoop Cache Snoop Cache W PU PU PU Illinois’s Protocol (The role of CE) CE：CleanExclusive CS：CleanSharable DE：DirtyExclusive I：Invalidate MainMemory Alargebandwidthsharedbus →DE PU

  35. Snoop Cache Snoop Cache R R PU PU PU Berkeley’s protocol MainMemory Alargebandwidthsharedbus US US PU Ownership→responsibility of write back OS:OwnedSharableOE:OwnedExclusive US:UnownedSharableI：Invalidated

  36. US Snoop Cache Snoop Cache W PU PU PU Berkeley’s protocol (A PU writes into) MainMemory Alargebandwidthsharedbus US →OE →I PU Invalidation is done like the basic protocol

  37. Snoop Cache I Snoop Cache R PU PU PU Berkeley’s protocol The line with US is not required to be written back MainMemory Alargebandwidthsharedbus OE →OS →US PU Inter-cache transfer occurs! In this case, the line with US is not consistent with the shared memory.

  38. CE CS Snoop Cache Snoop Cache PU PU PU Firefly protocol MainMemory Alargebandwidthsharedbus →CS PU CE：CleanExclusiveCS:CleanSharable DE:DirtyExclusive I：　Invalidate is not used!

  39. CS Snoop Cache Snoop Cache W PU PU PU Firefly protocol (Writes into the CS line) MainMemory Alargebandwidthsharedbus CS PU All caches and shared memory are updated → Like update type WriteThrough Cache

  40. CE Snoop Cache Snoop Cache Snoop Cache W PU PU PU Firefly protocol (The role of CE) MainMemory Alargebandwidthsharedbus →DE PU Like Illinoi’s, writing CE does not require bus transactions

  41. Snoop Cache Snoop Cache R R PU PU PU Dragon protocol MainMemory Alargebandwidthsharedbus UE US →US PU Ownership→Resposibility of write back OS:OwnedSharableOE:OwnedExclusive US:UnownedSharableUE:UnownedExclusive

  42. US Snoop Cache Snoop Cache W PU PU PU Dragon protocol MainMemory Alargebandwidthsharedbus US →OS PU Only corresponding cache line is updated. The line with US is not required to be written back.

  43. Snoop Cache Snoop Cache R PU PU PU Dragon protocol MainMemory Alargebandwidthsharedbus OE →OS → US PU Direct inter-cache data transfer like Berkeley’s protocol

  44. Snoop Cache Snoop Cache Snoop Cache W PU PU PU Dragon protocol (The role of the UE) MainMemory Alargebandwidthsharedbus UE →OE PU No bus transaction is needed like CE is Illinois’

  45. MOESI Protocol class Valid Owned Exclusive S：Sharable I： Invalid M: Modified E： Exclusive O： Owned

  46. MOESI protocol class • Basic：MSI • Illinois：MESI • Berkeley:MOSI • Firefly：MES • Dragon:MOES Theoretically well defined model. Detail of cache is not characterized in the model.

  47. Invalidate　ｖｓ．Update • The drawback of Invalidate protocol • Frequent data writing to shared data makes bus congestion　→ ping-pong effect • The drawback of Update protocol • Once a line shared, every writing data must use shared bus. • Improvement • CompetitiveSnooping • Variable Protocol Cache

  48. Invalidation C Snoop Cache Snoop Cache →D Ｗ PU PU PU Ping-pong effect（A PU writes into） MainMemory Alargebandwidthsharedbus C →I PU

  49. D Snoop Cache Snoop Cache →C R PU PU PU Ping-pong effect（The other reads out） MainMemory Alargebandwidthsharedbus I →C PU

  50. Invalidation C Snoop Cache Snoop Cache →D Ｗ PU PU PU Ping-pong effect（The other writes again） MainMemory Alargebandwidthsharedbus C →I PU

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