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Part 5 Fundamentals in Computer Design

Computer Architecture Slide Sets WS 2012/2013 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting. Part 5 Fundamentals in Computer Design. A hierarchy of definitions. A computer realizes with all his components a complete Hardware-Software-System.

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Part 5 Fundamentals in Computer Design

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  1. Computer Architecture Slide Sets WS 2012/2013 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 5 Fundamentals in Computer Design Computer Architecture – Part 5 –page 1 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  2. A hierarchy of definitions A computer realizes with all his components a complete Hardware-Software-System. The hierarchy of definitions of the system architecture can be expressed by a tree structure. System Architecture Software System Architecture (SSA) Hardware System Architecture (HSA) Computer Technology ComputerArchitecture Computer Organization,Macroarchitecture Processor Architecture,Instruction Set Architecture (ISA) Microarchitecture # processor # memory # bus functional units (ALU), register, caches, control unit, etc. instruction set register file addressing modes Computer Architecture – Part 5 –page 2 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  3. Hardware System Architecture - HSA • The hardware system architecture (HSA) describesthe organization and architecture of thecomputer and defines the hardwarecomponents for implementation. • The computer organization is partitioned in two levels: • macro level • micro level • At the macro level the global structure of thecomputer is defined. • The micro level instead describes the inner structureand implementation of the data path components,the busses, the caches, control unit etc. • The instruction set architecture (ISA) is regarded as partof the computer architecture. • The ISA describes the instruction set, the addressingmodes and models the register file. It is an abstractinterface between the software and hardware partof the computer. Software SystemArchitecture High Level Language Compiler Assembler Instruction Set architecture (ISA) Hardware System Architecture Organization Microarchitecture Computer Architecture – Part 5 –page 3 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  4. Instruction Set ArchitectureRISC / CISC • Instruction Set Architectures can be partitioned in: • RISC:Reduced Instruction Set Computerand • CISC:Complex Instruction Set Computer In modern microprocessors both paradigms are used more and more in combination. Computer Architecture – Part 5 –page 4 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  5. RISC-ISA A RISC-ISA consists of a simple structured instruction set, a comparable small number of different instructions, some few and simple addressing modes and a large register set. The instructions work on the internal registers only except some special load/store instructions to exchange register content with memory (Load-/Store-Architecture) The advantage of a simple instruction set is a high execution speed, efficient use of pipelining and an efficient decoding. Decoding is realized by a hardwired control unit Example: SUN SPARC instruction set Computer Architecture – Part 5 –page 5 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  6. RISC-ISA The disadvantage of the RISC-ISA is the high semantic gap between the High Level Language (HLL) and the simple assembler instructions. This high semantic gap has to be bridged by the compiler. Therefore the compiler is of high importance in the transformation from HLL to assembler in a RISC architecture. The length of the code increases as the instruction set of the computer become simpler. HLL- program Decoding by hardwired control unit Compiler Assembler control information Computer Architecture – Part 5 –page 6 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  7. CISC-ISA A CISC-ISA has a complex instruction set with a high number of different instructions (opcodes) and a lot of sophisticated addressing modes. All instructions can operate on registers or memory The CISC instruction set supports directly the constructs of a high level language. The compilation process is much easier and the length of the code become shorter, compared to a RISC instruction set. A very well-known CISC-ISA is the instruction set of the X86 family. Computer Architecture – Part 5 –page 7 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  8. CISC-ISA The main disadvantage of a CISC- ISA is a reduced execution speed, because of an inefficient use pipelining. The decoding is a very complex task and has to be solved by a micro programmed control unit. Microprogramming is of great importance in a CISC architecture. HLL- program micro programmed decoding (micro programmed control unit) Compiler Assembler Microcode control information Computer Architecture – Part 5 –page 8 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  9. ISA on today‘s processors To combine advantages of RISC ands CISC ISA, today’s processor use a two level approach: Example: Intel Pentium II, III, 4 (x86 CISC instruction set, internal RISC architecture) CISC ISA Processor Predecoder, Instruction Sequencer RISC ISA RISC Microarchitecture Computer Architecture – Part 5 –page 9 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  10. Overview of x86 based processors internal CISC internal RISC Computer Architecture – Part 5 –page 10 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  11. Tuple model for the design of a computer architecture The three domains of the tuple together with some levels of abstraction are structured in the well-known Gajski/Kuhn-Diagram. For the design of a processor or a complete embedded system, all domains and levels of the Gajski/Kuhn-diagram have to be considered. Today, nearly all transformations starting from the system specification are supported and automated by software tools. The principle of operation (functionality or behavior), the structure (digital circuits) and the chip integration (VLSI - Implementation) defines a model for designing a computer architecture. CA = (B, S, C) B = Behavior S = Structure C = Chip Computer Architecture – Part 5 –page 11 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  12. i-frankfurt.de/uploads/media/Part05-Fundamentals_in_Computer_Design_01.ppt+Gajski/Kuhn+uni+frankfurt&hl=de&gl=de&pid=bl&srcid=ADGEESgMWkC5kdzPUTc9pSNXlI0emWjrvwC4xxELr4-9C-0ai6LyIeRH1iN_tVgN59shud82GVewyJlWl-i-frankfurt.de/uploads/media/Part05-Fundamentals_in_Computer_Design_01.ppt+Gajski/Kuhn+uni+frankfurt&hl=de&gl=de&pid=bl&srcid=ADGEESgMWkC5kdzPUTc9pSNXlI0emWjrvwC4xxELr4-9C-0ai6LyIeRH1iN_tVgN59shud82GVewyJlWl- Views (domains) and levels of abstraction in the Y-Diagram of Gajski/Kuhn System level Algorithm level Behavior Structure Register Transfer level System- specification CPU, Memory Algorithm Logic level Processor, Subsystem Register-Transfer Model Module: ALU, Register, MUX circuit level Boolean Function Logic, Flip-flop Differential Equation Transistor Mask/ Polygon level cell level Macrocell level Floor plan level Chip level Geometry (Chip) Computer Architecture – Part 5 –page 12 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  13. Computer Architecture – Part 5 –page 13 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  14. Design of heterogeneous, embedded systems Processors or complete computersystems are more and more integrated in application systems. The computer, which realizes a Hardware/Software System (HW/SW), becomes “embedded” in the technical system. A computer designed to control such a technical environment is called Embedded System Technical environment like Hydraulics, Mechanics, … Digital HW AnalogHW Software Operating system Computer Architecture – Part 5 –page 14 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  15. Design of heterogeneous, embedded systems The design of such heterogeneous systems is a very complex task, because a lot of different models, descriptions and paradigms have to considered. The main procedure for the design of of embedded systems is the refinement from specification to implementation and the verification under the V-Model. Technical environment like Hydraulics, Mechanics, … Digital HW AnalogHW Software Operating system Computer Architecture – Part 5 –page 15 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  16. Design levels from the hardware point-of-view System Specification Modeling Simulation ValidationVerification Hardware ArchitectureIP Reuse ( Platform Design) Simulation Refinement Synthesis Silicon TechnologyIntegrated CircuitCMOS Computer Architecture – Part 5 –page 16 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  17. Design transformation steps For demonstrating the complexity of transformations in the design process, the transformation from the executable specification to the executable register transfer model is presented. Executablespecification parallelism Functional model delays (predicted) Timed functional model busses, communication Transaction specified model cycles Cycle based register transfer model Computer Architecture – Part 5 –page 17 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  18. The V-model of the design process The V model is a standard design model. The main procedure within the V-model is the refinement process. This refinement process means a stepwise -mostly interactive-transformation between levels of abstraction and views or domains of the Gajski-Diagram. The transformation steps are very complex tasks and mainly supported by software tools. One axis of the V defines the implementation and the other one the verification of the system. Between the axes of the V-model bypasses are possible. Computer Architecture – Part 5 –page 18 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  19. void P1(a, b){ y = a + b * c; …} virtualprototypes executablespecification models architecture V-model for design and verification Implementation Verification system complexity design complexity model complexity process complexity Computer Architecture – Part 5 –page 19 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  20. A generic system architecture For the design of complex embedded systems, a generic architecture of the Hardware/Software system is proposed. A generic architecture reduces the complexity of the design process for embedded systems. The mapping of the system specification to the architecture can be automated and supported by software tools, if a generic architecture exists. These tools are within the hardware synthesis, communication synthesis and software compilation. Computer Architecture – Part 5 –page 20 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  21. A generic system architecture • A generic architecture consists of: • one or multiple processor cores, • a communication- (switching) network • some digital hardware, mainly reconfigurable (FPGA). • In typical SOC applications this generic architecture is extended by further components as e.g.: • analog components, • sensors and actuators and/or • optical components. Computer Architecture – Part 5 –page 21 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  22. Design process for a generic chip architecture Hardware/Software- System-specification Hardware/Software- partitioning Hardware- synthesis Communication- synthesis Software- compilation FPGA FPGA Generic chip architecture Field Programmable Gate Arrays Processor Processor Processor FPGA Processor core Switching network Computer Architecture – Part 5 –page 22 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  23. Design languages • To simplify the combined hard- and software development approach, one could introduce ideas and experiences from software to hardware development: • Define a “High-Level-Hardware-Descriptionlanguage” introducing the following well known concepts from software development: object orientation inheritance reuse Computer Architecture – Part 5 –page 23 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  24. Design languages • Examples: • SystemC: Open System C Initiative • www.systemc.org • SystemVeriLog: System Verilog Organization • www.systemverilog.org • Cynthesizer: Forte Design Systems • www.ForteDS.com Computer Architecture – Part 5 –page 24 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  25. Design languages • SystemC ist very similar to C++ • Advantages: • Hardware components can be defined as objects with interfaces and functionality • Similar languages for soft- and hardware developmant enable synergetic effects • Common tools for soft- and hardware development can be used • Data exchange is simplified • High level verification is enabled by using formal high level languages Computer Architecture – Part 5 –page 25 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

  26. Design languages SystemC AMS (Analog Mixed Signals) is a SystemC extension. It supports the implementation of heterogeneous hardware/ software systems. Digital Hardware(discrete event) a + 1 • SystemC AMS • Will support combination of different models of computation and solvers • Intelligent, adaptive interfaces • C++ library • Modeling and refinement of communication • Discrete event simulation kernel • www.systemc-ams.org DSP+Software(SDF) Analog Circuits(CT-NET) Computer Architecture – Part 5 –page 26 of 25 – Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin Betting

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