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Trigger System of BES III

Trigger System of BES III. LIU Zhen’an Inst. of High Energy Physics, Beijing June 5-6 2002. Outline. Estimation of event rate Challenges to BESIII trigger Trigger principle Trigger scheme description Present status Summary. Estimation of event rate. Purpose of trigger system:

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Trigger System of BES III

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  1. Trigger System of BES III LIU Zhen’an Inst. of High Energy Physics, Beijing June 5-6 2002

  2. Outline • Estimation of event rate • Challenges to BESIII trigger • Trigger principle • Trigger scheme description • Present status • Summary BESIII Collab. Meet. Jun.5 2002,Beijing

  3. Estimation of event rate • Purpose of trigger system: • to accept all interested events • to rejects as much background as possible • DAQ is sustainable • With good design of MDC,TOF and EMC trigger, • we estimate that • total trigger rate • = good event rate (~2000, LBEPCII = 1  1033 cm-2 s-1) • + bhabha rate (~800,to be pre-scaled) • + cosmic event rate (<200,from 1500) • + beam background rate (<2000,from 13MHz) • = ~ 4000 Hz Fig:Backgrounds rate vs beam current At BESII/BEPC BESIII Collab. Meet. Jun.5 2002,Beijing

  4. The principle of BESIII trigger • Challenges to BESIII trigger design • High good event • High Backgrounds • Multi-bunches(93),small bunch spacing(8ns) • No dead time in trigger system • Pipeline processing must be used in trigger(Latch-process-decision mode not possible in 8ns) • Latency of trigger signal necessary BESIII Collab. Meet. Jun.5 2002,Beijing

  5. Time Reference Detector 0 s FEE pipeline Level 1 3.2s Readout buffer PowerPC switch Ev.Filter Farms Disk The principle of BESIII trigger(2)-data flow • Hardware trigger + software filter • FEE signal splitted: trigger + FEE pipeline • FEE pipeline clock 40MHz • Level 1(L1): 3.2s • FEE Control Logic checks L1 with FEE pipeline clock • L1 YES: moves pipeline buffer data • L1 No: • overwritten by new data BESIII FEE pipeline and Data flow BESIII Collab. Meet. Jun.5 2002,Beijing

  6. Block Diagram of BES III Trigger Global Trigger Logic TOF DISC Hit/Seg Count Track Match MDC DISC Track Seg. Finder Track Finder DAQ Energy Balance EMC TrigSum TC Sum Etotal Sum L1P Cluster Counting MU DISC Mu track CLOCK RF TTC 3.2 s BESIII Collab. Meet. Jun.5 2002,Beijing

  7. MDC Trigger-Signals Nswires 9096 N axial 4096 N stereo 5000 N layers 47 Nlaxial 19 Nlstereo 28 N pivot cells ax 96/120/208/312/336 N pivot cells st 48/72/160/184/236/264/288 N spcells/sector 32/16 BESIII Collab. Meet. Jun.5 2002,Beijing

  8. MDC trigger scheme (axial+stereo) 16Mod.,1crate 300 cards on FEE 16X2 BLT 36Mod.3crates 9096 TSF cards 2008 GLT TRK CNT GTSF Axial& stereo 16Mod.,1crate total 300 FEE cards, 5 crates with PowerPC 16 PTD BESIII Collab. Meet. Jun.5 2002,Beijing

  9. MDC trigger simulation • Private FORTRAN code • MDC structure + hits • Trigger scheme • Tasks: • Feasibility of trigger scheme • Trigger efficiency study • Wire in-efficiency influence study • Backgrounds rejecting ability study • Production of combination data • track-segment/track • PTD BESIII Collab. Meet. Jun.5 2002,Beijing

  10. TSF(Track Segment Finding) Pivot layer Ideal case: same cells,high Pt Real case simulation These data is used for TS finding BESIII Collab. Meet. Jun.5 2002,Beijing

  11. From O BLT GTSF R To Algorithm g 2 to1 GLT a t e Control IN DAQ OUT Mem Mem Mem Mem GTSF(TSF grouping) and BLT(Binary Link Track) Long track Short track BESIII Collab. Meet. Jun.5 2002,Beijing

  12. Momentum Discrimination(PTD) • Long track: • Reference layer SL11 • SL7,SL4 and SL3 • 3 / 4 or 4 / 4 • Short track: • Reference layer SL7 • SL4 and SL3 • 3 / 3 SL11 SL7 SL4 SL3 BESIII Collab. Meet. Jun.5 2002,Beijing

  13. Trigger efficiency study • With Weff.=96% and 3 / 4 requirement, 95% trigger effi. Achievable for Pt>150MeV track Configuration: Pt > 120 MeV We=1.0 We=0.95 BESIII Collab. Meet. Jun.5 2002,Beijing

  14. MDC background rejection • very good trigger efficiency for single artificial tracks with 3 / 4 • very good rejection of artificial cosmic rays 10cm away from vertax • Efficiency for physics channel to be done when input from GEANT based MDC simulation is available • Rejection for beam backgd to be done when inputs from beam background simulation is avalable BESIII Collab. Meet. Jun.5 2002,Beijing

  15. PMT 88 TOFB PMT PMT 88 TOFB PMT Leading Mean Leading Edge Disc Timer Edge Disc Leading Mean Leading Edge Disc Timer Edge Disc TOFE L &(L or L ) 1i 2i-1 2i+1 Discriminator TOF Trigger Master Trigger Hit count and Timing topology logic TOF Trigger 160 BESIII Collab. Meet. Jun.5 2002,Beijing

  16. EMC trigger Barrel: θ×φ=56×144 = 8064 Endcap: 120、120、120、96、 96、96、84、84、84 =1800 Basic trigger unit( trigger cell): sum of 24 crystals outputs BESIII Collab. Meet. Jun.5 2002,Beijing

  17. EMC Simulation • <20% difference acceptable • Gain adjustment for each crystal+PD+PreAmp chain • Trigger Cell should be at least 4X4 =16 crystals. • 4X6=24 is taken BESIII Collab. Meet. Jun.5 2002,Beijing

  18. BESIII EMC trigger scheme FEE 8ch sum Gain Adj. BESIII Collab. Meet. Jun.5 2002,Beijing

  19. From TOF Trigger From BEMC Trigger From MDC Trigger From EEMC Trigger TOF Track Distribution EEMC Track Distribution BEMC Track Distribution Input Signals Delay Input Signals Delay Input Signals Delay Input Signals Delay Barrel Track Match Eadcap Track Match Matched Track Count To Main Trigger Controller Track Matching scheme Total 40VME mod. 2 VME crates,2 PowerPC BESIII Collab. Meet. Jun.5 2002,Beijing

  20. Programmable Input Signal Delay Programmable Trigger Event Decision Trigger Conditions E-TYPE Programmable Pre-scale Multi-Scaler Reset Trigger EVT INIT TOF-T Trigger Controller L1 EMC-T CHK Trigger Signals Distribution EEMC-T To TRG Sub-system BUSY Clock Processor RF To Electronics TDC Global Trigger (GLT) • Inputs: sub-detector conditions • Time adjustment • trigger table • Pre-scaling of some event types BESIII Collab. Meet. Jun.5 2002,Beijing

  21. CLK GEVT L1 3s Tdead Tlife BUSY CHK TRG#=256 500ns Timing and handshaking with DAQ • Trigger pipeline clock • fRF= 499.8 MHz • f fRF /12  40MHz • Handshaking with DAQ BESIII Collab. Meet. Jun.5 2002,Beijing

  22. Present Status • Trigger scheme is drafted • Trigger simulation goes well, will go further with help from MC group • Development tools ready and working • Xilinx Foundation • Protel PCB • Rom programmer BESIII Collab. Meet. Jun.5 2002,Beijing

  23. Present Status(2) • Experiment Board for VME Module Design • Designed base on FPGA • Be used for testing other VME module’s functionality • Pipelined digital signal generator • Designed on Xilinx Foundation • Downloaded on Exp. Board • Signal Sequence Programmable • Signal length programmable • Readback Check • TTL/LVDS • high reliability BESIII Collab. Meet. Jun.5 2002,Beijing

  24. Present Status(3) • Clock Divider Experiment • VMS BUS extender and signal display • Digital programmable signal delay module of 16 channel is under designing. • MDC TSF board is modeled in FPGA with 32 inputs, and simulated, continue further • User Bus for trigger crate(VME P2) defined(draft) BESIII Collab. Meet. Jun.5 2002,Beijing

  25. Summary • Hardware trigger + software filter • L1 latency: changed to 3.2 s • Pipeline clock: 40 MHz • Monte Carlo simulation goes well and will continue • backgrounds, MDC, EMC trigger schemes • Preliminary design drafted • Some modules designed • Further/detailed designing undergoing • Welcome collaboration domestic and abroad BESIII Collab. Meet. Jun.5 2002,Beijing

  26. END THANK YOU ! WELCOME COMMENTS AND SUGGESTIONS BESIII Collab. Meet. Jun.5 2002,Beijing

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