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Bounded Sequential Equivalence Checking with Range-Equivalent Circuit, Node Merging , and NAR. Speaker: Chih-Chung Wang. Outline. Problem Formulation Introduction BSEC Node merging NAR Range-equivalent circuit Simple Algorithm Flowchart Experimental Result Future Work.
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Bounded Sequential Equivalence Checking with Range-Equivalent Circuit, Node Merging, and NAR Speaker: Chih-Chung Wang
Outline • Problem Formulation • Introduction • BSEC • Node merging • NAR • Range-equivalent circuit • Simple Algorithm Flowchart • Experimental Result • Future Work
Problem Formulation • Given: Two bounded sequential circuits, a bound k that using node merging and node addition and removal (NAR) optimizing will cost much time, where timeframe k-1 has been checked equivalent • Goal: Bounded sequential equivalence checking (BSEC) at timeframe koptimized by range-equivalent circuit replacement, node merging, and NAR
Bounded Sequential Equivalence Checking (BSEC) • Bounded: timeframe k • Typical BSEC • Miter construction • Unroll • Sequential → Combinational
Speeding Up • Circuit optimization • Node merging • Node addition and removal (NAR)
Speeding Up • Range-equivalent circuit • Range • Range-equivalent • Circuit of timeframe 0 to k-1 replacement
Resyn2 Original Optimized Construct miter pMiter Resyn2 NAR Optimize pMiterOpt timeframe 1 Resyn2 pFramePre Range-equivalent circuit replacement pRange timeframe k-1 Combine pFrame Resyn2 Optimize NAR pFrameOpt timeframe k Resyn2 SAT solver
Future Work • Solving the problems in Range-equivalent functions • Segmentation Fault • Run time decreasing • Tuning the functions of the program and testcases • Finding the bound of timeframe k and checking if range-equivalent circuit replacement can solve the problem • Optimizing the program