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Advisor: Dr. Chandra. Christopher Picard Michael Neuberg. Radar Basics CSU Facilities Hardware Accelerator Pawnee Update Next Semester Plans. National Weather Service. Radar- RAdio Detection And Ranging Transmits microwaves Elevation position, ∅ Azimuth Position, Ѳ.
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Advisor: Dr. Chandra Christopher Picard Michael Neuberg
Radar Basics • CSU Facilities • Hardware Accelerator • Pawnee Update • Next Semester Plans
National Weather Service • Radar- RAdio Detection And Ranging • Transmits microwaves • Elevation position, ∅ • Azimuth Position, Ѳ
Generates waveform of signals Old CHILL Dish and Antenna Constructing new dish location Builds up signal and transmits
Pawnee Facility GPS, DSP, etc Inside the Radome Signal Monitors and Generator
Ground Clutter Mitigation • Parametric Time Domain Method (PTDM) • Prevents the need for Fourier Transforms • Prevents signal Leakage • Problem • Requires calculating inverses and determinates of large matrices • Can not perform calculations in real time on standard CPU • Solution Requirements • Implement PTDM algorithm in real time
Graphics Card • Can perform multiple operations in parallel • Designed to optimize required matrix calculations • Nvidia CUDA • Compute Unified Device Architecture
Specification Multiprocessor 16 Memory 1.5 GB Shared Memory 16 KB per MP Registers 8192 per MP Threads 768 Memory Bandwidth 76.8 GB/Sec Hewlett Packard xw 9400 workstation
Replace synchros with optical encoders • Interface encoders and signal processor with FPGA • Design and build interface board • Improves radar tracking and positioning
Why replace synchros? • Stegmann ARS-20 absolute encoder • Rotating encoder disk • Enhanced resolution • Reduces noise and cost with less wires
Xilinx Spartan-3E FPGA • BASYS board • Printed Circuit Board • VHDL programming • Generate clock signal
Donations • CHILL Radar Facility • Encoders, development board, circuit board • ($1,250) • Hewlett Packard • xw 9400 workstation, 2 Quadro Fx 5600 • ($4,500)
Hardware Accelerator Tasks Start Date Finish Date Durations Get system setup and successfully run simple test CUDA programs. 12/10/07 1/21/08 6 Weeks Finish CUDA code that optimizes performance on real sample data 1/21/08 2/18/08 4 Weeks Integrate CUDA code with algorithm code. 2/18/08 3/31/08 6 Weeks Configure system to interact with radar interface and integrate system into site. 3/31/08 4/14/08 2 Weeks Hardware Update Tasks Start Date Finish Date Durations Finish programming interface for FPGA (Combine data, state machine, transmit) ------------- 1/27/08 12 Weeks Design printed circuit board 1/27/08 3/23/08 8 Weeks Build, test, and debug circuit board 3/23/08 4/13/08 3 Weeks
http://www.engr.colostate.edu/ece-sr-design/AY07/radar/index.htmlhttp://www.engr.colostate.edu/ece-sr-design/AY07/radar/index.html • Acknowledgments • Dr. Chandra • Jim George • Cuong Nguyen • Darryl Benally • Hewlett Packard