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Multi-Port SRAM Overview

Multi-Port SRAM Overview. Static Random Access Memory. Address. Address. Control. Control. Data. Data. Left Port. Right Port. Objectives. What are Multi-Port SRAMs? Why are they needed? Arbitration Features Busy Interrupt Semaphore Types: Dual-Port FourPort Bank Switchable

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Multi-Port SRAM Overview

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  1. Multi-Port SRAM Overview

  2. Static Random Access Memory Address Address Control Control Data Data Left Port Right Port Objectives • What are Multi-Port SRAMs? • Why are they needed? • Arbitration Features • Busy • Interrupt • Semaphore • Types: • Dual-Port • FourPort • Bank Switchable • SARAMs

  3. SRAM Dual-Port SRAM Static Random Access Memory ADDRESS Control DATA Static Random Access Memory Address Address Control Control Data Data Left Port Right Port SRAM vs. Multi-Port SRAM

  4. CPU SRAM Memory Bus DMA Hard Disk Controller Direct Memory Access Controller

  5. CPU Dual-Port SRAM CPU Multi-Port Memory Access

  6. Read / Write Read Read Read / Write Read Write or Write Read or Write Write Simultaneous Access OK! Problem!!!

  7. Data left Data right Memory Locations Control left Control right Address left Address right Busy Logic Busy left Busy right Dual Port SRAM Busy Flag • Compare Addresses • If addresses are the same: • Busy based on who was first • If simultaneous, busy logic will pick

  8. Write sets Right Int. Read clears Right Int. Right Interrupt Memory location Left Interrupt Memory location Read clears Left Int. Write sets Left Int. Interrupts • Interrupts controlled using two highest memory locations • Contents tells interrupted device what to do

  9. Semaphore CLEAR CLEAR CLEAR CLEAR Left Right CLEAR SET CLEAR SET Semaphores • One Semaphore contains two latches, one for each port. • Initially Clear • Left side requests then right side requests • Left side reads request granted, right side reads request denied • Left side clears, right side request may now be accepted

  10. Address Address Address Address PORT 1 PORT 3 Control Control Control Control Static Random Access Memory Data Data Data Data PORT 2 PORT 4 FourPort SRAM

  11. Address L Address R 8K x 16 8K x 16 8K x 16 8K x 16 Bank 1 Bank 2 Bank 3 Bank 0 Bank Addr L Bank Addr R Control L Control R Data L Data R Bank Select Bank-Switchable Dual-Port SRAM • Uses Standard SRAM • Bank accessible by only one port at a time • Bank select assigns banks to ports

  12. SARAM Static Random Access Memory Clock Address Control Control Data Data Random Access Port Sequential Access Port Sequential Access RAM (SARAM) • One port accesses memory locations randomly • Second port accesses memory locations sequentially.

  13. Static Random Access Memory Address Address Control Control Data Data Left Port Right Port Summary • Multiple device high speed memory access • No DMA required • Arbitration may be required • Types: • Dual Port • FourPort • Bank Switchable • Sequential Access RAM

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