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Multi-Port Memory Products

Multi-Port Memory Products. Product Line Update. Presentation Outline. Why IDT for Multi-Ports? 2.5V Dual-Ports IDT’s x36 Multi-Port Family Bank-Switchable™ Dual-Port Family IDT’s Synchronous FourPort™ Roadmaps for Multi-Ports. NEW. Updates. = Best in Industry.

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Multi-Port Memory Products

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  1. Multi-PortMemoryProducts Product Line Update

  2. Presentation Outline • Why IDT for Multi-Ports? • 2.5V Dual-Ports • IDT’s x36 Multi-Port Family • Bank-Switchable™ Dual-Port Family • IDT’s Synchronous FourPort™ • Roadmaps for Multi-Ports NEW Updates

  3. = Best in Industry Why Look to IDT for Multi-Port Memory Solutions? • Superior Track Record on Multi-Ports • IDT is the Industry Leader in Multi-Ports…for +15 Years • Set nearly all Performance/Feature Standards for Industry • Breadth of Portfolio…Over 150 Multi-Port Products • Unmatched Performance and Range of Solutions • Width: x8, x9, x16, x18, x36 • Speed: up to 200 MHz sync, 10 ns async • 2ports x 36 bits x 200 MHz =14 Gb/sec • Density: 8 Kb up to 9 Mb • Upgrade Path: x36 Family supports 0.5 Mb to 9 Mb+ • Voltage: 5V, 3.3V, 2.5V, 3.3V with selectable 3.3V/2.5V I/Os • Functionality: Bank-Switchables, FourPorts, SARAMs…

  4. Mobile/Wireless Core/Metro 24% Storage Area 27% Networks Enterprise 7% Broadband 16% 8% Miscellaneous 18% Multi-Ports: Markets Served Segment Sample Application BTS, BTS-C, RNC, MSC, Terminals Switches, Routers (ATM, FR, TDM) Storage (RAID), Directors/Switches VPN, VoPN, 100 Mbps ES DSLAM Graphics, Military, Medical, etc.

  5. Multi-Port Products Dual-Ports Bank-Switchable™ Dual-Ports FourPort™ • Async • Sync • SARAM™ • Async • Sync • Async • Sync

  6. SARAM FourPort Multi-Port Portfolio Synchronous Asynchronous Special Functions 5V x8: 256Kb to 1Mb x9: 36Kb to 1Mb x16: 256Kb to 1Mb x18: 576Kb to 1Mb 5V x8: 8Kb to 1Mb x9: 18Kb to 1Mb x16: 32Kb to 1Mb x18: 72Kb to 1Mb Bank Switchable 3.3V x8: 8Kb to 1Mb x16: 32Kb to 1Mb x18: 72Kb to 1Mb 3.3V x8: 8Kb to 1Mb x9: 36Kb to 1Mb x16: 32Kb to 1Mb x18: 72Kb to 1Mb • Future Directions • Sync 2.5V/1.8V x36 at 9 Mb, 18 Mb • Tailored functions for target markets • Specialized configurations for specific applications New 2.5V x8: 64Kb to 128Kb x9: 72Kb to 144Kb x16: 64Kb to 128Kb x18: 72Kb to 144Kb New 2.5V x9: 72Kb to 144Kb x18: 72Kb to 144Kb New New 3.3V/2.5V* x18: 576Kb to 9Mb x36: 576Kb to 9Mb 3.3V/2.5V* x18: 1Mb to 9Mb x36: 1Mb to 9Mb * - Core is 2.5V or 3.3V, I/Os are selectable 3.3V/2.5V

  7. 2.5V Dual-Ports • True Dual-Port Architectures • Advanced Functions • High Performance • Function-compatible with 5V and 3.3V offerings • Excellent mix of cost and function

  8. New 2.5V Dual-Ports • 2.5V power supply for both core and I/Os • Fully pin and function-compatible with corresponding 5V and 3.3V devices in TQFP packages • Also available in 10mm x 10mm fpBGA to minimize boardspace requirements

  9. New 2.5V Dual-Ports • 8 asynchronous configurations... as fast as 20 ns • 70T05 8Kx8 70T06 16Kx8 • 70T15 8Kx9 70T16 16Kx9 • 70T24 4Kx16 70T25 8Kx16 • 70T34 4Kx18 70T35 8Kx18 • 4 synchronous configurations... as fast as 83 MHz • 70T9159 8Kx9 70T9169 16Kx9 • 70T9349 4Kx18 70T9359 8Kx18

  10. x36 Multi-Port Family • True Dual-Port and Bank-Switchable Architectures • Advanced Functions • High Performance • Dense Storage Capacity • Excellent Upgrade Path

  11. = New Release = Future product x36 Multi-Port Solutions Common Packages/Footprints for Powers, Grounds, I/Os, and Controls V = 3.3V core with selectable 3.3V/2.5V I/O T = 2.5V core with selectable 3.3V/2.5V I/O

  12. A True Family of Dual-Ports • Fastest Speeds • Sync at 200 MHz • Async at 10 ns tAA • Multiple Depth/Width Combinations • Density from 0.5Mb up to 9Mb • X36, x18, x9 (@2Mb) configurations • Common package for x36, x18 in BGA • JTAG • Selectable 3.3V / 2.5V I/Os

  13. = 0.5 Mb = 1 Mb = 2 Mb = 4 Mb = 9 Mb BF208 fpBGA Roadmap to Higher Density* 15 mm 15 mm All other pins are common footprint (sync, async, x36, x18) for I/Os, Controls, and Power/Ground *BF208 shown… DR208, BC256, DD144, and PK128 provide similar upgrade capabilities

  14. = VDD or VSS Signal Pins grouped to outer three rows to facilitate board routing, improve thermal performance 1.0 mm pitch BGA • 1.4 mm thick • 256-ball (16 x 16) • Additional NCs for future upgrades 17 mm 17 mm

  15. x36 Multi-Port Solutions

  16. JTAG Support • Defined by IEEE 1149.1 • 5 pins - TDI, TDO, TMS, TCK, TRST# • Our x36 Family devices support: • BYPASS, IDCODE, EXTEST, HIGHZ, and SAMPLE/PRELOAD • Internally biased to turn JTAG off if pins are left floating (or can tie/hold TRST# low) • We are JTAG compliant, not just ‘compatible’

  17. New 9 Mb Async True Dual-Ports • x36 and x18 configurations, 9 Mb and 4 Mb • 2.5V core, selectable 2.5V/3.3V I/Os • 10 ns Access • Traditional Advanced Functions • Busy (Master and Slave modes) • Interrupts • Semaphores • New Function • Sleep Mode

  18. Asynchronous Sleep Mode • Sleep Mode... • Offset higher current draw associated with higher chip densities • Increased compatibility with advanced memory controllers • How does the Sleep Mode work? • Asynchronous Input Signal which deselects RAM • Inputs can toggle without affecting Sleep current (IZZ) • All Outputs in High-Z state • Timing Parameters • tZZS (Sleep Mode Set Time) = tAA (Min.) (i.e., 10 ns on fastest device) • tZZR (Sleep Mode Recovery Time) = tAA (Min.)

  19. New 9 Mb Sync True Dual-Ports • x36 and x18 configurations, 9 Mb and 4 Mb • 2.5V core, selectable 2.5V/3.3V I/Os • 200 MHz operations • New Functions • Sync Interrupts (Mailbox function) • Collision Detection • Sleep Mode

  20. Synchronous Mailbox Interrupt • New Interrupt function... • Facilitate port-to-port coordination (‘hand-shaking’) • Has been implemented without degradation of performance • Improves compatibility with async multi-port offerings • How does the Interrupt work? • Similar function to our existing Asynchronous parts EXCEPT Output Flag is Synchronous • Address Location 3FFFE  Mailbox Interrupt for Left port (INTL) • Address Location 3FFFF  Mailbox Interrupt for Right port (INTR) • Timing Parameters (For 200 MHz) • tINS (Interrupt Flag Set Time) = 6 ns • tINR (Interrupt Flag Reset Time) = 6 ns

  21. Synchronous Collision Detection • Collision Detection... • Developed in response to customer requests • Has been implemented with no degradation of performance • Very useful for customers doing burst accesses • What is it? • Synchronous Output Flag which notifies the user that a simultaneous access has occurred at one of the preceding address locations • Both Ports Reading  NO FLAG ON EITHER PORT • 1 Port Reading & 2nd port Writing  FLAG ON READING PORT • Both ports Writing  FLAG ON BOTH PORTS • Flag is pipelined and will be output two cycles later • Timing Parameters (For 200 MHz) • tCOLS (Collision Flag Set Time) = 3.4 ns, Same as tCD2 • tCOLR (Collision Flag Reset Time) = 3.4 ns, Same as tCD2

  22. Read Read MEMORY ARRAY Port “A” Read / Write Port “B” Read / Write Write Read / Write Traditional Sync Functionality

  23. Read Read MEMORY ARRAY Port “A” Port “B” Flag Flag Flag Flag Write Write Read Read Write Write Collision Detection

  24. Synchronous Sleep Mode • Sleep Mode... • Offset higher current draw associated with higher chip densities • Increased compatibility with advanced memory controllers • How does the Sleep Mode work? • Asynchronous Input Signal (does not have to align on clock edge) which deselects RAM • Clocks can continue running without affecting Sleep current (IZZ) • All Outputs in High-Z state • All Inputs allowed to Toggle • Timing Parameters • tZZSC (Sleep Mode Set Cycles) = 2 cycles (Min.) • tZZRC (Sleep Mode Recovery Cycles) = 3 Cycles (Min.)

  25. Bank-Switchable Dual-Port Family • Innovative Architecture • More Aggressive Cost-per-Bit • Higher Performance • Denser Storage Capacity • Excellent Upgrade Path

  26. Definition What is a Bank-Switchable Dual-Ported SRAM? • True SRAM core, surrounded by multiplex circuits • Memory internally partitioned into banks • Simultaneous access to separate banks only • Intermediate step between muxed SRAM and full Dual-Port - Densest and Lowest cost-per-bit Dual-Port • x36 offerings pin-compatible with full Dual-Ports

  27. Memory Array Memory Array Bank 0 Bank 1 LEFT PORT CONTROLS LEFT PORT CONTROLS RIGHT PORT CONTROLS RIGHT PORT CONTROLS Bank 2 Bank n Right Port Access Left Port Access Right Port Access Left Port Access COMPARISON: BSDP and Standard Dual-Port Standard Dual-Port • Two ports access one common RAM array • Simultaneous Access from both ports to the same cell • Memory arbitration at the cell level • >2x the bandwidth of SRAM • Bank-Switchable DP SRAM • Two ports access Banks of common RAM array • Simultaneous Access from both ports to separate banks • Memory arbitration at the Bank level • >2x the bandwidth of SRAM • Highest Density and Lowest Price Dual-Port solution in the industry!

  28. BA0L - BA5L BA0R - BA5R A0L - A11L A0R - A11R = Cannot Match during Access = Don’t Care Synchronous BSDP Upgrade to BSDP functionality: • Mux is now steered by bank address pins, not by external bank select pins • Increased number of banks (now 64 banks, regardless of density) Like earlier generation, sync BSDP relies on external arbitration • Each internal bank is true SRAM • Simultaneous access to same bank blocks both ports 64 Banks MUX

  29. Sync FourPort • True FourPort™ Architecture • Advanced Functions • High Performance • Dense Storage Capacity • Increased Port Count

  30. Port Functions (each port): Dual chip enables Independent clock input Full boundary counter Maskable counter register Address readback function Counter-based interrupt Mailbox interrupt x9 byte controls Device Functions: JTAG Memory Built-in Self-Test (MBIST) Master Reset Two Package Options BC-256 (1.00 mm pitch) BG-272 (1.27mm pitch) Controls Controls Inputs/Outputs Inputs/Outputs Synchronous FourPort™ 64Kx18 3.3V 200 MHz Controls Controls Inputs/Outputs Inputs/Outputs IDT70V5388

  31. Synchronous FourPort™ - IDT70V53883.3V -- 200 MHz -- 64Kx18 • Pin and function-compatible with QuadPort in 272-pin BGA • Independent clock domains • Advanced counter functions (masks, counter readback) • Interrupts • MBIST and JTAG • Significant performance enhancements • Full support of advanced counter functions at 0.5Mb and 1Mb (QP supports 1Mb only) • MBIST at 200 MHz in 14.8M cycles (QP at 50 MHz in 31.2M cycles) • Operating current at 133 MHz: IDT: 300 mA typical, 460 mA max QP: 350 mA typical, 700 mA max Power reduction of 15% to 30% in like operating conditions • 200 MHz operations per port, compared to QP max of 133 MHz 40% higher bandwidth (14 Gbps vs. 9.6 Gbps) • Smaller package option in the 256-pin BGA BG-272 (IDT, QP)BC-256 (IDT) 27mm x 27mm, 1.27mm pitch 17mm x 17mm, 1.00mm pitch 729mm2 289mm2 Boardspace savings of nearly 60%

  32. Switching Write any port, read from any other port Separate, independent clock domains and frequencies Mailbox and specialized counter controls Ability to combine ports (e.g., one x36 port to two x18 ports) Data muxing and demuxing One port write, many read and/or many write, one read Maskable counters Multi-component shared memory storage to support CPUs, DSPs, NPUs, FPGAs, ASICs... Independent, simultaneous, random access from all ports at frequencies up to 200 MHz Byte controls to facilitate bus matching Mailbox functions FourPort Applications BG-272 BC-256

  33. IDT - the Proven Leader • The undisputed leader in market share • The technology leader with the world’s highest performance multi-ports • We continue to set the standards • Density • Performance • Features IDT is committed toPowering What’s Next

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