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Manufacturing Process -II

EE4271 VLSI Design. Dr. Shiyan Hu Office: EERC 518. Manufacturing Process -II. Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Challenge. 193 nm. Illumination source. 45 nm. Mask. Objective Lens.

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Manufacturing Process -II

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  1. EE4271VLSI Design Dr. Shiyan Hu Office: EERC 518 ManufacturingProcess -II Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

  2. Challenge 193nm Illumination source 45nm Mask Objective Lens Aperture Wafer 2

  3. Mask v.s. Printing Layout 0.25µ 0.18µ 0.13µ 90-nm 65-nm What you design is NOT what you get! 3

  4. Motivation Chip design cannot be fabricated Gap Lithography technology: 193nm wavelength VLSI technology: 45nm features Lithography induced variations Impact on timing and power Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported.

  5. Gap: Lithography Tech. v.s. VLSI Tech. 28nm, tolerable distortion: 2nm 193nm Increasing gap  Printability problem (and thus variations) more severe! 5

  6. Design Rules

  7. Design Rules • Interface between designer and process engineer • Guidelines for constructing process masks • Unit dimension: Minimum line width • scalable design rules: lambda parameter • absolute dimensions (micron rules)

  8. Lambda Rule • Every distance in layout rules is specified by lambda • Given a process, lambda is set to a specific value. • Process technology is defined using minimum line width. 0.25um technology means minimum line width is 0.25um. Lambda=minimum line width/2. • For a 0.25um process, lambda=0.125um • In practice, scaling is often not linear. • Industry usually uses micron rule and lambda rule is used only for prediction/estimation of the impact of technology scaling to a design.

  9. Layers in 0.25 mm CMOS process

  10. Intra-Layer Design Rules 4 Metal2 3 Rules are used to mitigate fabrication error

  11. Transistor Layout

  12. Layout Editor

  13. Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

  14. Some Packages

  15. Wire Bonding (not printed) Bond wire

  16. Imprinted Tape-Automated Bonding Disadvantage: Must place I/O pins at the specific locations (i.e., around the boundary on the die).

  17. Flip-Chip Bonding • Flip-Chip places connection across the chip rather than around boundary. • The bond wire is replaced with solder bump balls directly placed on the die surface • Chip is flipped upside down • Carefully align to package • Heat to melt solder bump balls

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