Manufacturing Process

1. Manufacturing Process http://www-micrel.deis.unibo.it/CEDLA

2. General info • Date esami: • Giugno • Luglio • Sito per le slide o il materiale delle esercitazioni: http://www-micrel.deis.unibo.it/CEDLA • Tutor del corso: ing. Elisabetta Farella. • Per contattare il tutor: tutorcedla@gmail.com

3. The MOS Transistor

4. The MOS Transistor Polysilicon Aluminum

5. Cross-Section of CMOS Technology

6. Dual-well approach A Modern CMOS Process

7. Circuit Under Design – Symbolic representation

8. Its Layout View

9. The Manufacturing Process

10. Sliced wafers The Silicon Wafer Molten Silicon Bath and Czochralski method Single-crystal ingot • Important metric: defect density of the base material • 10-30 cm diameters, 1mm thickness • Doping: 2x1021 impurities/m3 Seed crystal Diamond saw 2:00 – 4:15

11. Clean Rooms

12. Photolithography • 1. Oxidation layering • 2. Photoresist coating • 3. Stepper exposure • 4. Photoresist development and bake • 5. Acid Etching • 6. Spin, rinse, and dry • 7. Various process steps • 8. Photoresist removal (or ashing)

13. Photo-Lithographic Process optical mask oxidation photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step

14. Example: Patterning of SiO2 Done in parallel on the entire wafer Chemical or plasma etch Si-substrate Hardened resist SiO 2 (a) Silicon base material Si-substrate Photoresist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate Hardened resist (b) After oxidation and deposition SiO of negative photoresist 2 Si-substrate UV-light Patterned (e) After etching optical mask Exposed resist SiO 2 Si-substrate Si-substrate (f) Final result after removal of resist (c) Stepper exposure Scaling is getting mask-based steps more and more challenging

15. Recurring processing step (1)DIFFUSION and ION IMPLANTATION Doping recurs many times. Two approaches: • DIFFUSION IMPLANTATION: wafers in quartz tube in a heated furnace (900-1100 °C);  dopants in gas diffuse in the exposed surface vertically and horizontally.  more dopants on the surface than deeper in the material • ION IMPLANTATION (+ annealing): dopants introduced by directing a beam of purified ions over semiconductor surface.  Ions accelerations  deepness of penetration; Beam current and exposure time  dosage.  lattice damage. Repair by ANNEALING step (heating based) Diffusion furnace The magnets used to control the ion beam A wafer handling tray in ion implantation

16. Recurring processing step (2)DEPOSITION Repetitively, material is deposited over the wafer (buffering, insulating, etc.). Different techniques depending on materials • Chemical vapor deposition (CVD): gas-phase reaction with energy supplied by heat (850°C). Ex. Si3N4 • Chemical deposition: Silane gas over heated wafer coated with SiO2 = Polysilicon non-crystalline amorphous material • Sputtering for Alluminium interconnect layers. Alluminium evaporated in vacuum, heated by electron-beam or ion-beam bombarding. • … etc.

17. Recurring processing step (3)ETCHING To selectively form patterns (wires, contact holes) • Wet etching – use of acid or basic solutions • Dry or plasma etching – well defined directionality (sharp vertical contours) PLANARIZATION To ensure a flat surface a chemical-mechanical planarization (CMP) step is included before deposition of extra-metal layer on top of insulating SiO2

18. Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts CMOS Process at a Glance Create contact and via windows Deposit and pattern metal layers

19. p-epi (a) Base material: p+ substrate with p-epi layer + p Si N 3 4 SiO (b) After deposition of gate-oxide and 2 p-epi sacrificial nitride (acts as a buffer layer) + p (c) After plasma etch of insulating trenches using the inverse of the active area mask p + CMOS Process Walk-Through

20. SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V adjust implants Tp p (f) After p-well and V adjust implants Tn CMOS Process Walk-Through

21. poly(silicon) (g) After polysilicon deposition and etch n + + p (h) After n + source/drain and p + source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. CMOS Process Walk-Through

22. Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via’s, deposition and patterning of second layer of Al. CMOS Process Walk-Through

23. Advanced Metallization

24. Advanced Metallization

25. Design Rules

26. 3D Perspective Polysilicon Aluminum

27. Design Rules • Interface between designer and process engineer • Guidelines for constructing process masks • Unit dimension: Minimum line width • scalable design rules: lambda parameter • absolute dimensions (micron rules)

28. Layer Color Representation Well (p,n) Yellow Active Area (n+,p+) Green Select (p+,n+) Green Polysilicon Red Metal1 Blue Metal2 Magenta Contact To Poly Black Contact To Diffusion Black Via Black CMOS Process Layers

29. Layers in 0.25 mm CMOS process

30. Intra-Layer Design Rules 4 Metal2 3

31. Transistor Layout

32. Vias and Contacts

33. Select Layer

34. CMOS Inverter Layout

35. Layout Editor

36. Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

37. V DD 3 Out In 1 GND Stick diagram of inverter Sticks Diagram • Dimensionless layout entities • Only topology is important • Final layout generated by “compaction” program

38. Packaging

39. Packaging Requirements • Electrical: Lowparasitics • Mechanical: Reliable and robust • Thermal: Efficient heat removal • Economical: Cheap • Size: small

40. Bonding Techniques

41. Tape-Automated Bonding (TAB)

42. Flip-Chip Bonding

43. Package-to-Board Interconnect (SMD) (c) Ball Grid Array

44. Package Types

45. Package Parameters

46. Multi-Chip Modules