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Active Glitch Elimination in FPGAs: A Power-Saving Technique

This research presents an active glitch elimination technique for FPGAs, reducing power consumption by 18% while minimizing area overhead and critical-path delay. The technique uses programmable delay circuits to align arrival times, resulting in significant power savings without requiring changes to the existing CAD flow.

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Active Glitch Elimination in FPGAs: A Power-Saving Technique

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  1. An Active Glitch Elimination Technique for FPGAs by Julien Lamoureux, Guy Lemieux, and Steven J.E. Wilton University of British Columbia Funding provided by Altera and NSERC

  2. Context of this Research • FPGAs use a lot of power • Dynamic power still dominates Source: Altera Stratix II Study (99 Circuits)

  3. Overview • Reducing power in FPGAs by minimizing glitching • Using programmable delay circuits to align arrival times • Results: • 18% power savings • 5% area overhead • 1% critical-path delay overhead • No changes to the existing CAD flow

  4. What is glitching? • Unnecessary transitions • Generated by uneven arrival times • Propagated by certain gates

  5. How much glitching is there?

  6. Context of this Research 1/3 of Dynamic Power!

  7. Idea Use programmable delay circuits to lineup arrival times.

  8. Idea Use programmable delay circuits to lineup arrival times.

  9. ASIC vs. FPGA • ASIC • Circuit and delays are known before fabrication • Fixed delay circuits can be used • FPGA • Circuit and delays are unknown • Delay circuits needed to be programmable • Location of delays must be carefully considered

  10. Where should the delays go? • Option 1: Global Routing • Option 2: Logic Blocks (LABs)

  11. Where in the LAB?

  12. Where in the LAB?

  13. Where in the LAB? Too Expensive?

  14. 4 Schemes

  15. Programmable Delay Circuit

  16. Programmable Delay Circuit Biased PMOS Biased NMOS

  17. Programmable Delay Circuit Biased PMOS Biasing Circuit Biased NMOS

  18. Calibrating Scheme 1

  19. Calibrating Scheme 1 Three parameters: • Number of delay circuits per LUT • Maximum delay of the delay circuit • Minimum delay of the delay circuit

  20. Number of delay circuits per LUT

  21. Number of delay circuits per LUT

  22. Number of delay circuits per LUT

  23. Number of delay circuits per LUT

  24. K-1 Number of delay circuits per LUT

  25. Maximum Delay 4ns

  26. Maximum Delay 6ns

  27. Maximum Delay 8ns

  28. Maximum Delay 8ns

  29. Minimum Delay Increment 100ps

  30. Minimum Delay Increment 200ps

  31. Minimum Delay Increment 300ps

  32. 250ps Minimum Delay Increment

  33. Glitch Elimination Results

  34. Glitch Elimination Results

  35. Overhead

  36. Overhead Area • count minimum width transistor areas • 5.3 %

  37. Overhead Area • count minimum width transistor areas • 5.3 % Tcrit • VPR delay + HSPICE delay circuit • 0.21 %

  38. Overhead Area • count minimum width transistor areas • 5.3 % Tcrit • VPR delay + HSPICE delay circuit • 0.21 % Power • VPR power + HSPICE delay circuits • 0.45 %

  39. Overall Results

  40. Final Power Savings

  41. Summary • Proposed an active glitch elimination technique for FPGAs • Examined how to implement the technique • Reduced power by 18% with only 5% area and 1% speed • Proposed technique requires little or no modifications to the CAD flow or routing architecture

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