Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

1. Compact Reconfigurable Binary-Decision-Diagram Logic Circuiton a GaAs Nanowire Network Speaker: Chang-En Chiang Advisor: Dr. Chun-Yao Wang 2012/6/1

2. Outline • Introduction • Reconfigurable BDD logic circuit • Basic concepts • Example • Conclusion

3. Introduction • An approach to implementing flexibility in BDD circuits has been reported; however, the methodology is rather complex [1]. • In this paper, a reconfigurable BDD logic circuit having universality even with its simple structure is proposed. • The proposed BDD circuit can implement any logic function. [1] S. Eachempati, V. Saripalli, V. Narayanan, and S. Datta, “Reconfigurable Bdd-based Quantum Circuits,” in Proc. Int. Symp. on Nanoscale Architectures, 2008, pp. 61-67.

4. Basic concepts • The BDD is a representative scheme of a logic function that uses a directed graph instead of logic gates. • We describe a reconfigurable BDD circuit based on Shannon’s expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. • In the proposed circuit, nanowire branches are electrically connected or disconnected in accordance with a program that provides reconfiguration capability.

5. Example

6. Reconfigurable BDD logic circuit • If the switch can be programmed in a short time, dynamic reconfiguration of the circuit becomes possible. • The numbers of node devices and programmable switches for n-input variable functions are 1 and , respectively. • When the number of implemented functions is reduced, the size of the circuit can be decreased by using the reduced-order BDD technique.

7. Conclusion • The authors described a reconfigurable BDD logic circuit based on Shannon’s expansion of a Boolean function and its graphical representation on a nanowire network. • The proposed circuit architecture has a simpler structure and is more compact than the previous reconfigurable BDD and conventional CMOS look up table. • Correct outputs and dynamically reconfigured operation were obtained in the fabricated circuit by suitable programming.

8. An Enhanced Mapping Approach to SET Arrays Considering Fabric Constraint Speaker: Chang-En Chiang Advisor: Dr. Chun-Yao Wang 2012/6/1

9. Outline • Introduction • Previous work • Variable reordering • Product term reordering • LTG-based product term computation • Experimental result • Conclusion • Future work

10. Introduction • SET: Single-Electron Transistor • An SET array can be presented as a graph composed of hexagons • All sloping edges areconfigurable • short, open, active (high or low) • Active edges at the same row are controlled by a single variable

11. Example • An example of a XOR b: active high a a active low short open b b

12. Mapping constraint • Fabric constraint • (high, low) and (low, high) cannot simultaneously appear in a row • For simplification, we allow only one of (high, low) and (low, high) to appear in an SET array 0110 0102 1122

13. Threshold logic • Threshold logic is an alternative to Boolean logic • The input output relation of a threshold gate is defined as follows: • Example: y = a’(b + c) 1 -2 1 1 a b c f

14. Grouping • A threshold logic gate can be divided into many groups. • An input whose weight is equal to the threshold value of the objective gate as a single group • The remaining inputs are separated as another group. a b c d e f 5 5 3 2 1 1 5 f

15. Critical input • An input is critical if this group will become useless after removing the input Critical input a b c 3 2 1 1 5 f d

16. Problem formulation • Given: A Boolean function • Objective: Mapping the product terms into an SET array with optimized area considering fabric constraint

17. Outline • Introduction • Previous work • Variable reordering • Product term reordering • LTG-based product term computation • Experimental result • Conclusion • Future work

18. The overall mapping flow of prior work current detector 18 0010 01-0 100- 11-- 0 1 1

19. Ladder shape • We use a heuristic method to make the shape of mapping result like a ladder Different expansion level share

20. Mapping approach • Variable reordering • Product term mapping ordering considering fabric constraint • Mapping constraint relaxation • Expansion method 01001 00221 11221 10001 10121 10100 11000 10022 11012 11122 Previous Work Our approach

21. Outline • Introduction • Previous work • Variable reordering • Product term reordering • LTG-based product term computation • Experimental result • Conclusion • Future work

22. Product term computation (Gate) Give an LTG LTG has two or more groups? yes no Gate modification LTG has a critical input? yes no Decide value of some bits by critical vector which has the least number of bit 1 Decide value of some bits no Done? End yes

23. Product term computation (Gate) This LTG has a critical input b c d a b c d f 3 2 1 1 2 1 1 5 2 f

24. Product term computation (Gate) The new LTG can be divided into groups b c d c d a b c d f f 3 2 1 1 2 1 1 1 1 5 2 2 f

25. Product term computation (Gate) The new LTG has a critical input b c d c d a b c d f f 3 2 1 1 2 1 1 1 1 5 2 2 f

26. Product term computation (Gate) c d a b c d c d c d 3 2 2 1 f 5 2 1 f 2 2 1 f 2 1 1 5

27. Product term computation (Network) LTG Network Gate computation Gate Scanning for each level Start from PO No Conflict Checking Primary Input? Yes End

28. Product term computation (Network)

29. The structure of a threshold network • The effectiveness of LTG-based product term computation depends on the structure of a threshold network. • We attempt to use the ILP-based synthesis method to generate the threshold network having the least number of LTG.

30. The structure of a threshold network n1 b c d a b c d 3 1 1 1 3 1 1 1 3 f 3 3 3 f a

31. Overall mapping flow Input: a Boolean function of each PO. Product term computation Compute product term by BDD-based method. Compute product term by LTG-based method. Choose the smaller number of product term between BDD-based and LTG-based method. Variable reordering and product term reordering. Map product terms into an SET array with mapping constraint relaxation. Output: an SET array.

32. Outline • Introduction • Previous work • Variable reordering • Product term reordering • LTG-based product term computation • Experimental result • Conclusion • Future work

33. Experimental results • Experiment • Compare the hybrid approach and BDD approach • 25 circuits from MCNC benchmark and 6 from IWLS 2005

34. Experimental results

35. Outline • Introduction • Previous work • Variable reordering • Product term reordering • LTG-based product term computation • Experimental result • Conclusion • Future work

36. Conclusion • We proposed an enhanced mapping approach minimizing the area of SET array • We proposed an hybrid approach which can reduce the number of product terms.

37. Outline • Introduction • Previous work • Variable reordering • Product term reordering • LTG-based product term computation • Experimental result • Conclusion • Future work

38. Future work • Verify our mapping result • Write paper

39. ISSUE Boolean function: ab+cd+e e a b a b 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 f 1 1 1 1 c d f c d e

40. ISSUE Boolean function: ab+cd+e a b e 2 2 1 1 1 1 2 2 2 1 1 a b 2 2 2 1 1 f f e c d c d