Introduction to Computer Architecture and Design Ji Chen Section : T TH 1:00PM – 2:30PM

1. Introduction to Computer Architecture and Design Ji Chen Section : T TH 1:00PM – 2:30PM Prerequisites: ECE 4436

2. Instructor: Ji Chen Email: jchen18@uh.edu Tel: (713)-743-4423 Office: W328 Office Hour: T TH 2:30-3:30 or by appointment TA: None

4. Course Contents • Introduction, basic computer organization • Instruction formats, instruction sets and their design • ALU design: Adders, subtracters, logic operations • Multiplication, division, floating point arithmetic • Datapath design • Control design: Hardwired control, microprogrammed control • Pipelining • Memory systems • I/O

5. Web: http://www.egr.uh.edu/courses/ece/ECE5367/ Grading Academic Honesty Statement

6. Computer Organization and Design: The Hardware/Software Interface by David A. Patterson, John L. Hennessy, 3rd edition Required NOT REQUIRED

7. Home works/quiz: There will be several graded homework/lab assignments. Home works turned in late will be accepted only under extraordinary circumstances. Labs:  Laboratory assignments may be worked in teams of two (2); however, there should be no collaboration between teams . .  Lab assignments turned in late will be penalized 25 points for each calendar day.  Both students in a team will receive the same grade for the project. Projects: Teams of four (4): describe computer architecture of a modern technology Exams: two mid-term exams, and one final exam.  A missed exam will result in a grade of zero  Let me know immediately if you have any situation Final Exam - TBD Grading: Your final grade will be computed as follows:

8. Control Datapath • Since 1946 all computers have had 5 components Processor Input Memory Output

9. TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 MBus Module SuperSPARC Floating-point Unit L2 $ CC Integer Unit MBus DRAM Controller MBus control M-S Adapter L64852 Inst Cache Ref MMU Data Cache STDIO SBus serial kbd SCSI Store Buffer SBus DMA mouse Ethernet audio RTC Bus Interface SBus Cards Floppy Message Bus (Mbus)

10. Computer Architecture Application Operating System Compiler Firmware Instruction Set Architecture Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Layout • Coordination of many levels of abstraction • Under a rapidly changing set of forces • Design, Measurement, and Evaluation

11. Forces on Computer Architecture Technology Programming Languages Applications Cleverness Computer Architecture Operating Systems History

12. Mixed-Signal

13. Arithmetic Single/multicycle Datapaths IFetch Dcd Exec Mem WB µProc 60%/yr. (2X/1.5yr) 1000 CPU IFetch Dcd Exec Mem WB “Moore’s Law” WB IFetch Dcd Exec Mem 100 Processor-Memory Performance Gap:(grows 50% / year) IFetch Dcd Exec Mem WB Performance 10 DRAM 9%/yr. (2X/10 yrs) DRAM 1 Pipelining 1980 1998 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1999 2000 I/O Time Memory Systems Where are We Going?? ECE 5367 Spring 08 

14. Performance • Purchasing perspective • Given a collection of machines, which has the • Best performance ? • Least cost ? • Best performance / cost ? • Design perspective • Faced with design options, which has the • Best performance improvement ? • Least cost ? • Best performance / cost ? • Both require • basis for comparison • metric for evaluation • Our goal: understand cost & performance implications of architectural • choices

15. DC to Paris Speed Passengers Throughput (pmph) 6.5 hours 610 mph 470 286,700 3 hours 1350 mph 132 178,200 Two Notions of “Performance” Plane Boeing 747 Concorde • Which has higher performance? • Time to do the task (Execution Time) • – execution time, response time,latency • Tasks per day, hour, week, sec, ns. .. (Performance) • – throughput, bandwidth • Response time and throughput often are in opposition

16. Definitions • Performance is in units of things-per-second • bigger is better • If we are primarily concerned with response time • performance(x) = 1 execution_time(x) • " X is n times faster than Y" means • Performance(X) • n = ---------------------- • Performance(Y)

17. Example • Time of Concorde vs. Boeing 747? • Concord is 1350 mph / 610 mph = 2.2 times faster • = 6.5 hours / 3 hours • Throughput of Concorde vs. Boeing 747 ? • Concord is 178,200 pmph / 286,700 pmph = 0.62 “times faster” • Boeing is 286,700 pmph / 178,200 pmph = 1.60 “times faster” • Boeing is 1.6 times (“60%”) faster in terms of throughput • Concord is 2.2 times (“120%”) faster in terms of flying time We will focus primarily on execution time for a single job Lots of instructions in a program => Instruction throughput important!

18. CPU = Seconds = Instructions x Cycles x Seconds Performance Program Program Instruction Cycle

19. Amdahl's Law Speedup due to enhancement E: ExTime w/o E Performance w/ E Speedup(E) = -------------------- = --------------------- ExTime w/ E Performance w/o E Suppose that enhancement E accelerates a fraction F of the task by a factor S and the remainder of the task is unaffected then, ExTime(with E) = ((1-F) + F/S) x ExTime(without E) Speedup(with E) = 1 (1-F) + F/S

20. Base Machine Op Freq Cycles CPI(i) % Time ALU 50% 1 .5 23% Load 20% 5 1.0 45% Store 10% 3 .3 14% Branch 20% 2 .4 18% 2.2 Typical Mix How much faster would the machine be if a better data cache reduced the average load time to 2 cycles? How does this compare with using branch prediction to save a cycle off the branch time? What if two ALU instructions could be executed at once?