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On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board

On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board. Rob Jones, Roman Machan, Tahsin Lin, and Ed Leventhal ASRC Aerospace Corp. 6303 Ivy Lane, Suite 800 Greenbelt, MD 20770 {robert.jones, roman.machan, tahsin.lin, ed.leventhal}@akspace.com. Key Points.

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On the Model-centric Design and Development of an FPGA-based Spaceborne Downlink Board

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  1. On the Model-centric Design and Developmentof an FPGA-based Spaceborne Downlink Board Rob Jones, Roman Machan, Tahsin Lin, and Ed LeventhalASRC Aerospace Corp. 6303 Ivy Lane, Suite 800Greenbelt, MD 20770 {robert.jones, roman.machan, tahsin.lin, ed.leventhal}@akspace.com Jones

  2. Key Points • About the SMART approach to model-centric engineering design and development • Uses formal (mathematical and therefore unambiguous) descriptions of a system throughout its development • Petri nets, queuing networks, data- and control-flow graphs, finite automata, Markov chains, or user-defined formalisms • Provides model checking and numerical analysis • Facilitates concept formulation, trade studies, and rapid prototyping before committing to hardware and software • Successfully applied to an FPGA-based downlink system designed for space applications • Example models constructed using Petri nets Jones

  3. p1 p1 t1 t1 p2p3 t3 t2 p2 p3 t4 t2t3 t4 t2 t3 p4p3 p2p5 t4 p4 p5 t3 t2 p4p5 t5 t5 Petri Net Underlying State Machine Model • Bipartite graph ofplaces and transitions connected by arcs • Marking of placeswith tokens providesstate • Transitions are activewhen sufficient tokensare present or absentfrom input places • Transitions thenfire, thus removingtokens from inputplaces and depositing them tooutput places • Firing may be delayed randomly or deterministically token transition marking fires place Jones

  4. The SMART Approach Stochastic Model-Checking Analyzer for Reliability and Timing (SMART) Capture – Well-defined system requirements and design specification Validation – Modeling the right system Verification – Modeling the system right Analysis – Performance tradeoffs Realization – Allocate functions to resources Testing – Cases, coverage, and acceptance Iteration – Repeat steps as necessary to refine modeling and design details Integration – Aided by well-defined interfacesand architecture Deployment – Preservation and maturation of models aid documentation, operation, and maintenance Requirements High-level Petri Net Validation Model Analysis and Testing Analytical Model Checking Simulation Intermediate SystemC VHDL FPGA Execution Low-level Integrate Jones

  5. Downlink Dataflow and Queuing 32-bitInput Data from CompactPCI Bus Interrupt on Input Queue status or queuing errors High-speed Downlink Board Downlink Ready when Input Queue is at most 1/4 full USES Bypass OutputData 15 bits 80 Mb/s 20 MB/s 10 MB/s USES USESQueue VCDU Function OutputQueue CADUFunction LVDS DRVR Input Function SerialBit Stream 66 MW/s 20 MS/s(S=samples) 2K16 4K8 LSBsQueue InputQueue Reed-Solomon Encoder LSBs 4K8 1K32 Jones

  6. Input Arrival and Buffering Access Bus word (w) = 16 bits Transfers from Sensor Module Downlink Ready BurstArrival ¼Bi + 1 Block Buffer Write (32 bits) 1K DownlinkInput Queue Next Block 2 (words) 1 cycle 5 cycles 16 Mw/s burst10 Mw/s average Delay Preempt Active Transfer Done Other Use Busy UseBus Idle State of PCI Bus Resume Inactive Jones

  7. Input Preprocessing ¾Bu • Each 2 KB of data is encoded into a compressed sourcepacket for CCSDS transport • 16-bit words are unpacked from PCI input • LSBs removed, queued, and later rejoined with packet data within each Virtual Channel Data Unit (VCDU) UnpackInput Process begins with sufficient data Prevents USES Queue overflow Remove LSB Sample Data USES Queue Input Queue ¼Bi+1 20 Msamp/s USES 2 VCDU Function Word Data 2 cycles 8 10 Mw/s LSBs LSBsQueue 1 cycle Write LSBs 1 cycle Jones

  8. USES Data Compression IDbits EndPac Rice Block EvaluateBlock N·(J - #(Ref)) #(EndPac) J Encoding Bit Info Begin Code Read BlkRef (b) Samples 16 #(Ref) (1-b) Output Reduce Insert Ref Block Count #(EndPac) Data Ready N #(Code) Reference Count Write Delay End Packet RefPac USES Queue cond(0 < #(Code) < 16, 1, 0) Jones

  9. VCDUHeader PacketPrimaryHeader PacketSecondaryHeader Packet Data Space 8 bytes 6 bytes 1 byte 1,085 bytes VCDUs ¾Bo WriteVCDUHeader 8 Data Queue 1cycle 16x8 bits StartNewVCDU WriteData OutputQueue Data Space Writing Packet PrimaryHeader Start NewPacket HeaderLength 1092 6 Complete(variable-length)Data Packet Create(variable-length)Data Packet 1cycle WriteHeader 8cycles State ofWritingPackets tk 2tk AuxQueue PacketLength tk Jones

  10. Data Packets AuxQueue # # WritePacketSecondaryHeader ¾Bd 1 cycle DataQueue 1 cycle First Complete(Compressed)Data Packet LSBsQueue ¾Bd 2 cycles WriteLSBs Second 2 USESQueue 128 WriteUSESPacket ¾Bd Third 2 StartNewPacket Packet Length tk(Packet Length) Last tk(Packet Length) Jones

  11. Maximum Entropy Rate14.7 bits/word 5.9 bits/word mean 3.5 bits/word minimum Downlink Model Analysis 25 (1) Input Queue 20 15 Entropy Rate (bits per word)of IR data, 0.6 wave no. around ZPD (4) Output to transmitter Mean 10 (2) USES Queue 5 (3) Output Queue Jones

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